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参数资料
| 型号： | MC68331CFC16B1 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 16 MHz, MICROCONTROLLER, PQFP132 |
| 封装： | 0.950 X 0.950 INCH, 0.025 INCH PITCH, PLASTIC, QFP-132 |
| 文件页数： | 26/90页 |
| 文件大小： | 481K |
| 代理商： | MC68331CFC16B1 |
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MOTOROLA
MC68331
32
MC68331TS/D
ADDR[23:11] —Base Address Field
This field sets the starting address of a particular address space. The address compare logic uses only
the most significant bits to match an address within a block. The value of the base address must be a
multiple of block size. Base address register diagrams show how base register bits correspond to ad-
dress lines.
3.5.4 Option Registers
The option registers contain eight fields that determine timing of and conditions for assertion of chip-
select signals. For a chip-select signal to be asserted, all bits in the base address register must match
the corresponding internal upper address lines, and all conditions specified in the option register must
be satisfied. These conditions also apply to providing DSACK or autovector support.
CSORBT, the option register for CSBOOT, contains special reset values that support bootstrap opera-
tions from peripheral memory devices.
The following bit descriptions apply to both CSORBT and CSOR[10:0] option registers.
MODE —Asynchronous/Synchronous Mode
0 = Asynchronous mode selected (chip-select assertion determined by internal or external bus con-
trol signals)
1 = Synchronous mode selected (chip-select assertion synchronized with ECLK signal)
In asynchronous mode, the chip select is asserted synchronized with AS or DS.
The DSACK field is not used in synchronous mode because a bus cycle is only performed as a syn-
chronous operation. When a match condition occurs on a chip select programmed for synchronous op-
eration, the chip select signals the EBI that an ECLK cycle is pending.
BYTE —Upper/Lower Byte Option
This field is used only when the chip-select 16-bit port option is selected in the pin assignment register.
The following table lists upper/lower byte options.
Block Size Field
Block Size
Address Lines Compared
000
2 K
ADDR[23:11]
001
8 K
ADDR[23:13]
010
16 K
ADDR[23:14]
011
64 K
ADDR[23:16]
100
128 K
ADDR[23:17]
101
256 K
ADDR[23:18]
110
512 K
ADDR[23:19]
111
1 M
ADDR[23:20]
CSORBT —Chip-Select Option Register Boot ROM
$YFFA4A
15
14
13
12
11
10
9
6
5
4
3
1
0
MODE
BYTE
R/W
STRB
DSACK
SPACE
IPL
AVEC
RESET:
0
1
0
1
0
1
0
CSOR[10:0] —Chip-Select Option Registers
$YFFA4E–$YFFA76
15
14
13
12
11
10
9
6
5
4
3
1
0
MODE
BYTE
R/W
STRB
DSACK
SPACE
IPL
AVEC
RESET:
0
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC68331CFC20 | 制造商:Freescale Semiconductor 功能描述: |
| MC68331CFC20B1 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Freescale Semiconductor 功能描述: |
| MC68331CFC25 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Freescale Semiconductor 功能描述: |
| MC68331CFC25B1 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Freescale Semiconductor 功能描述: |
| MC68331CFV16 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:User’s Manual |
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