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参数资料
| 型号： | MC68331CFC25B1 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 25 MHz, MICROCONTROLLER, PQFP132 |
| 封装： | 0.950 X 0.950 INCH, 0.025 INCH PITCH, PLASTIC, QFP-132 |
| 文件页数： | 50/90页 |
| 文件大小： | 481K |
| 代理商： | MC68331CFC25B1 |
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MOTOROLA
MC68331
54
MC68331TS/D
QTEST — QSM Test Register
$YFFC02
QTEST is used during factory testing of the QSM. Accesses to QTEST must be made while the MCU
is in test mode.
QILR determines the priority level of interrupts requested by the QSM and the vector used when an in-
terrupt is acknowledged.
ILQSPI — Interrupt Level for QSPI
ILQSPI determines the priority of QSPI interrupts. This field must be given a value between $0 (inter-
rupts disabled) to $7 (highest priority).
ILSCI — Interrupt Level of SCI
ILSCI determines the priority of SCI interrupts. This field must be given a value between $0 (interrupts
disabled) to $7 (highest priority).
If ILQSPI and ILSCI are the same nonzero value, and both submodules simultaneously request inter-
rupt service, QSPI has priority.
QIVR determines which two vector numbers in the exception vector table are to be used for QSM inter-
rupts. The seven MSB of a user-defined vector number ($40–$FF) must be written into the INTV field
during initialization. The value of INTV0 is supplied by the QSM when an interrupt service request is
acknowledged.
During an interrupt-acknowledge cycle, INTV[7:1] are driven on DATA[7:1] IMB lines. DATA0 is negated
for an SCI interrupt and asserted for a QSPI interrupt. Writes to INTV0 have no meaning or effect.
Reads of INTV0 return a value of one.
At reset, QIVR is initialized to $0F, which corresponds to the uninitialized interrupt vector in the excep-
tion table.
5.3.2 Pin Control Registers
The QSM uses nine pins, eight of which form a parallel port (PORTQS) on the MCU. Although these
pins are used by the serial subsystems, any pin can alternately be assigned as general-purpose I/O on
a pin-by-pin basis.
Pins used for general-purpose I/O must not be assigned to the QSPI by register PQSPAR. To avoid
driving incorrect data, the first byte to be output must be written before DDRQS is configured. DDRQS
must then be written to determine the direction of data flow and to output the value contained in register
PORTQS. Subsequent data for output is written to PORTQS.
QILR — QSM Interrupt Levels Register
$YFFC04
15
14
13
11
10
8
7
0
ILQSPI
ILSCI
QIVR
RESET:
0
QIVR — QSM Interrupt Vector Register
$YFFC05
15
8
7
0
QILR
INTV
RESET:
0
1
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相关代理商/技术参数 |
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| MC68331CFV16 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:User’s Manual |
| MC68331CFV20 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:User’s Manual |
| MC68331CPV16 | 功能描述:IC MCU 32BIT 16MHZ 144-LQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:M683xx 其它有关文件:STM32F101T8 View All Specifications 特色产品:STM32 32-bit Cortex MCUs 标准包装:490 系列:STM32 F1 核心处理器:ARM? Cortex?-M3 芯体尺寸:32-位 速度:36MHz 连通性:I²C，IrDA，LIN，SPI，UART/USART 外围设备:DMA，PDR，POR，PVD，PWM，温度传感器，WDT 输入/输出数:26 程序存储器容量:64KB（64K x 8） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:10K x 8 电压 - 电源 (Vcc/Vdd):2 V ~ 3.6 V 数据转换器:A/D 10x12b 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:36-VFQFN，36-VFQFPN 包装:托盘 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名称:497-9032STM32F101T8U6-ND |
| MC68331CPV16B1 | 制造商:Rochester Electronics LLC 功能描述:32BIT MCU,GPT,SIM,QSM - Bulk |
| MC68331CPV20 | 制造商:Rochester Electronics LLC 功能描述:32BIT MCU,GPT,SIM,QSM - Bulk |
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