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| 型号： | MC68332AMEH20 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 5/88页 |
| 文件大小： | 0K |
| 描述： | IC MCU 32BIT 20MHZ 132-PQFP |
| 标准包装： | 36 |
| 系列： | M683xx |
| 核心处理器： | CPU32 |
| 芯体尺寸： | 32-位 |
| 速度： | 20MHz |
| 连通性： | EBI/EMI，SCI，SPI，UART/USART |
| 外围设备： | POR，PWM，WDT |
| 输入/输出数： | 15 |
| 程序存储器类型： | ROMless |
| RAM 容量： | 2K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 132-BQFP 缓冲式 |
| 包装： | 托盘 |
| 产品目录页面： | 733 (CN2011-ZH PDF) |
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MC68332
MOTOROLA
MC68332TS/D
13
2.5 Signal Function
TSC
SIM
Input
—
TXD
QSM
Output
—
XFC
SIM
Input
—
XTAL
SIM
Output
—
Table 6 MCU Signal Function
Signal Name
Mnemonic
Function
Address Bus
ADDR[23:0]
24-bit address bus
Address Strobe
AS
Indicates that a valid address is on the address bus
Autovector
AVEC
Requests an automatic vector during interrupt acknowledge
Bus Error
BERR
Indicates that a bus error has occurred
Bus Grant
BG
Indicates that the MCU has relinquished the bus
Bus Grant Acknowledge
BGACK
Indicates that an external device has assumed bus mastership
Breakpoint
BKPT
Signals a hardware breakpoint to the CPU
Bus Request
BR
Indicates that an external device requires bus mastership
System Clockout
CLKOUT
System clock output
Chip Selects
CS[10:0]
Select external devices at programmed addresses
Boot Chip Select
CSBOOT
Chip select for external boot start-up ROM
Data Bus
DATA[15:0]
16-bit data bus
Data Strobe
DS
During a read cycle, indicates when it is possible for an external
device to place data on the data bus. During a write cycle, indi-
cates that valid data is on the data bus.
Data and Size Acknowledge
DSACK[1:0]
Provide asynchronous data transfers and dynamic bus sizing
Development Serial In, Out,
Clock
DSI, DSO,
DSCLK
Serial I/O and clock for background debugging mode
Crystal Oscillator
EXTAL, XTAL
Connections for clock synthesizer circuit reference;
a crystal or an external oscillator can be used
Function Codes
FC[2:0]
Identify processor state and current address space
Freeze
FREEZE
Indicates that the CPU has entered background mode
Halt
HALT
Suspend external bus activity
Instruction Pipeline
IFETCH
IPIPE
Indicate instruction pipeline activity
Interrupt Request Level
IRQ[7:1]
Provides an interrupt priority level to the CPU
Master In Slave Out
MISO
Serial input to QSPI in master mode;
serial output from QSPI in slave mode
Clock Mode Select
MODCLK
Selects the source and type of system clock
Master Out Slave In
MOSI
Serial output from QSPI in master mode;
serial input to QSPI in slave mode
Port C
PC[6:0]
SIM digital output port signals
Peripheral Chip Select
PCS[3:0]
QSPI peripheral chip selects
Port E
PE[7:0]
SIM digital I/O port signals
Port F
PF[7:0]
SIM digital I/O port signals
Port QS
PQS[7:0]
QSM digital I/O port signals
Table 5 MCU Signal Characteristics (Continued)
Signal Name
MCU Module
Signal Type
Active State
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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