9- 4
MC68341 USER’S MANUAL
MOTOROLA
Table 9-1. QSPM Pin Summary
Pin
Mode
QDDR Bit
Pin Function
Master
0
Serial Data Input to QSPI
MISO
1
Output Value from QPDR
Slave
0
Input Value to QPDR
1
Serial Data Output from QSPI
Master
0
Input Value to QPDR
MOSI
1
Serial Data Output from QSPI
Slave
0
Serial Data Input to QSPI
1
Output Value from QPDR
Master
0
Input Value to QPDR
QSPI Pins
SCK
1
Clock Output from QSPI
Slave
0
Clock Input to QSPI
1
Output Value from QPDR
Master
0
Input (May Cause Mode Fault)
PCS0/SS
1
Output Selects Peripherals
Slave
0
Input Selects the QSPI
1
Output Value from QPDR
Master
0
Input Value to QPDR
PCS1
1
Output Selects Peripherals
Slave
0
Input Value to QPDR
1
Output Value from QPDR
X = QDDR bit ignored.
The QSPM pin control registers—QDDR, QSPM pin assignment register (QPAR), and
QSPM port data register (QPDR)—affect pins being used as general-purpose I/O pins.
The QSPI control register 0 (SPCR0) has one bit that affects pins employed as general-
purpose output pins. Within this register the wired-OR mode (WOMQ) control bit
determines whether MISO, MOSI, SCK, PCS1, and PCS0 function as open-drain output
pins or as normal output pins, regardless of their use as general-purpose I/O pins or as
QSPI output pins.
9.4 REGISTERS
Registers of the QSPM are divided into three categories: QSPM global registers, QSPM
pin control registers, and QSPI submodule registers. The QSPI registers are defined in 9.5
QSPI Submodule. Writes to unimplemented bits have no meaning or effect, and reads
from unimplemented bits always return a logic zero value.
In the registers discussed in the following pages, the numbers in the upper right-hand
corner indicate the offset of the register from the base address specified in the module
base address register (MBAR) in the SIM41. The numbers above the register description
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.