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MC68341 USER’S MANUAL
MOTOROLA
0 = User access
Because the QSPM contains a mix of supervisor and user registers, AACK
returns for accesses with either supervisor or user mode, and the bus cycle
remains internal. If a supervisor-only register is accessed in user mode, the
module responds as if an access had been made to an unimplemented register
location.
SUPV defines the assignable QSPM registers as either supervisor-only data
space or unrestricted data space.
Bits 6–4—Not Implemented
IARB—Interrupt Arbitration Identification Number
Each module that generates interrupts, including the QSPM, must have an IARB field.
The value in this field is used to arbitrate for the IMB when two or more modules
generate simultaneous interrupts of the same priority level. No two modules can share
the same IARB value. The reset value of the IARB field is $0, which prevents the QSPM
from arbitrating during an interrupt acknowledge cycle (IACK). The IARB field should be
initialized by system software to a value between $F (top priority) and $1 (lowest
priority). Otherwise, any interrupts generated are identified by the CPU as spurious.
9.4.2.2 QSPM TEST REGISTER (QTEST). QTEST is used in testing the QSPM.
Accesses to QTEST must be made while the MC68341 is in test mode.
QTEST
$802
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9876543210
0
TSBD
RSVD
TQS
M
RSVD
RESET:
0000000000000000
TSBD—SPI Test Scan Path Select
1 = Enable delay to SCK scan path
0 = Enable SPI baud clock scan path
RSVD—Reserved
TQSM—QSPM Test Enable
1 = Enable QSPM to send test scan paths
0 = Disable scan path
9.4.2.3 QSPM INTERRUPT LEVEL REGISTER (QILR). The QILR determines the priority
level of interrupts requested by the QSPM and the vector used when acknowledging an
interrupt. This register may be accessed only when the CPU is in supervisor mode.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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