参数资料
型号: MC68360EM25
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 7 CHANNEL(S), 2M bps, SERIAL COMM CONTROLLER, PQFP240
封装: PLASTIC, QFP-240
文件页数: 9/14页
文件大小: 47K
代理商: MC68360EM25
4
MC68360 PRODUCT INFORMATION
MOTOROLA
QUICC ARCHITECTURE OVERVIEW
The QUICC is 32-bit controller that is an extension of other members of the Motorola M68300 family. Like
other members of the M68300 family, the QUICC incorporates the intermodule bus (IMB). (The MC68302 is
an exception, having an M68000 bus on chip.) The IMB provides a common interface for all modules of the
M68300 family, which allows Motorola to develop new devices more quickly by using the library of existing
modules. Although the IMB definition always included an option for an on-chip 32-bit bus, the QUICC is the
first device to implement this option.
The QUICC is comprised of three modules: the CPU32+ core, the SIM60, and the CPM. Each module
utilizes the 32-bit IMB. The MC68360 QUICC block diagram is shown in Figure 1.
EXTERNAL
BUS
INTERFACE
SYSTEM
PROTECTION
SIM 60
CPU32+
CORE
IMB (32 BIT)
RISC
CONTROLLER
SYSTEM
I/F
2.5-KBYTE
DUAL-PORT
RAM
DRAM
CONTROLLER
AND
CHIP SELECTS
CPM
PERIODIC
TIMER
CLOCK
GENERATION
OTHER
FEATURES
BREAKPOINT
LOGIC
JTAG
COMMUNICATIONS PROCESSOR
FOUR
GENERAL-
PURPOSE
TIMERS
INTERRUPT
CONTROLLER
OTHER
FEATURES
TIMER SLOT
ASSIGNER
SEVEN
SERIAL
CHANNELS
TWO
IDMAs
FOURTEEN SERIAL
DMAs
Figure 1. QUICC Block Diagram
CPU32+ Core
The CPU32+ core is a CPU32 that has been modified to connect directly to the 32-bit IMB and apply the
larger bus width. Although the original CPU32 core had a 32-bit internal data path and 32-bit arithmetic
hardware, its interface to the IMB was 16 bits. The CPU32+ core can operate on 32-bit external operands
with one bus cycle. This allows the CPU32+ core to fetch a long-word instruction in one bus cycle and to
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