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RISC Timer Tables
MOTOROLA
MC68360 USER’S MANUAL
7-13
NOTE: Boldfaced items are initialized by the user.
TM_BASE. The actual RISC timers are located by the user as a small block of memory in
the dual-port RAM. TM_BASE is the offset from the beginning of dual-port RAM where that
block resides. The user should allocate 4 bytes at TM_BASE for each timer used (64 bytes
at TM_BASE if all 16 timers are used). If less than 16 timers are used, the timers should
always be allocated in ascending order (RISC timer 0, RISC timer 1, etc.) to save space. For
example, if the user only needs two timers, then 8 bytes are required at location TM_BASE
as long as the user only enables RISC timer 0 and RISC timer 1.
NOTE
TM_BASE should always be aligned to a long-word boundary
(i.e., evenly divisible by 4).
TM_ptr. This value is used exclusively by the RISC to point to the next timer to be accessed
in the timer table. It should not be modified by the user.
R_TMR. This value is used exclusively by the RISC to store the mode of the timer: one-shot
(bit is zero) or restart (bit is one). R_TMR should not be modified by the user. The SET
TIMER command should be used instead.
R_TMV. This value is used exclusively by the RISC to store whether a timer is currently
enabled. A bit is a one if the corresponding timer is enabled. R_TMV should not be modified
by the user. The SET TIMER command should be used instead.
TM_cmd. This value is used as a parameter location when the SET TIMER command is
issued. The user should write this location prior to issuing the SET TIMER command. This
parameter is defined as follows:
V—Valid
This bit should be set to enable the timer and cleared to disable the timer.
R—Restart
This bit should be set for an automatic restart or cleared for a one-shot operation of the
timer.
Table 7-2. RISC Timer Table Parameter RAM
Address
Name
Width
Description
Timer Base + 00
TM_BASE
Word
RISC Timer Table Base Address
Timer Base + 02
TM_ptr
Word
RISC Timer Table Pointer
Timer Base + 04
R_TMR
Word
RISC Timer Mode Register
Timer Base + 06
R_TMV
Word
RISC Timer Valid Register
Timer Base + 08
TM_cmd
Long
RISC Timer Command Register
Timer Base + 0C
TM_cnt
Long
RISC Timer Internal Count
31
30
29
20
19
16
15
0
V
R
—
TIMER NUMBER
TIMER PERIOD (16 BITS)