Electrical Characteristics
10-12
MC68360 USER’S MANUAL
MOTOROLA
10.9BUS OPERATION AC TIMING SPECIFICATIONS (CONTINUED
NOTES:
1. All AC timing is shown with respect to 0.8 V and 2.0 V levels unless otherwise noted.
2. This number can be reduced to 5 ns if strobes have equal loads.
3. If multiple chip selects are used, the CS width negated (#15) applies to the time from the negation of a heavily load-
ed chip select to the assertion of a lightly loaded chip select.
4. These hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKO1 on fast
termination reads. The user is free to use either hold time for fast termination reads.
5. If the asynchronous setup time (#47) requirements are satisfied, the DSACK low to data setup time (#31) and
DSACK
low to BERR low setup time (#48) can be ignored. The data must only satisfy the data-in to CLKO1 low
setup time (#27) for the following clock cycle: BERR must only satisfy the late BERR low to CLKO1 low setup time
(#27A) for the following clock cycle.
6. To ensure coherency during every operand transfer, BG will not be asserted in response to BR until after cycles of
the current operand transfer are complete and RMC is negated.
7. In the absence of DSACK , BERR is an asynchronous input using the asynchronous setup time (#47).
8. During interrupt acknowledge cycles, the processor may insert up to two wait states between states S0 and S1.
9. These specs are for Synchronous Arbitration only. ASTM=1.
10.These CS specs are for TRLX=0. If RAS and RASDD are connected together, reduce max value of RAS spec-
ification by 1.5ns.
11.These CS specs are for TRLX=1. If RAS and RASDD are connected together, reduce max value of RAS spec-
ification by 1.5ns.
12.These CS specs are for CSNTQ=0.
13.These CS specs are for CSNTQ=1; or RAS specs for DRAM accesses.
14.These specs are read cycles with parity check and PBEE=1.
15.These specs are read cycles with parity check and PBEE=0,PAREN=1.
16.These RAS specs are for page miss case.
17. These specifications only apply to CS/RAS pins.
18. This specification applies to non fast termination cycles. In fast termination cycles, the BERR signal must be negated
by 20ns after negation of AS, DS.
Num.
Characteristic
Symbol
3.3 V/5.0 V
5.0V
Unit
25.0 MHz
33.34MHz
Min
Max
Min
Max
88
CLKO1 High to IFETCH High Impedance
tIFZ
035
0
26.25
ns
89
CLKO1 High to IFETCH Valid
tIF
035
0
26.25
ns
90
CLKO1 High to PERR Asserted
tCHPA
020
0
15
ns
91
CLKO1 High to PERR Negated
tCHPN
020
0
15
ns
92
Minimum Vcc Ramp-Up Time At Power-On Reset
tRMIN
5-
5
-
ms