Baud Rate Generators (BRGs)
7-106
MC68360 USER’S MANUAL
desired parity mode. Changes in the parity mode may be accomplished in the UART proto-
col specific mode register (PSMR).
NOTES
The SCC associated with this BRG must be programmed to
UART mode. The SCC must have the TDCR and RDCR bits in
the general SCC mode register set to the 16
× option for the au-
tobaud function to operate correctly.
The input clock that is supplied to the BRG in autobaud mode
should be as fast as possible to improve the accuracy of the start
bit measurement. Input frequencies such as 1.8432MHz,
3.68MHz, 7.36MHz and 14.72MHz should be used.
For autobaud to operate sucessfully, the SCC performing the
autobaud function must be connected to the baud rate generator
for that SCC. In other words, for SCC2 to correctly perform the
autobaud function, it must be clocked by BRG2. Also, for the
SCC to correctly detect an autobaud lock and an interrupt to be
generated, the SCC must receive three full Rx clocks from the
BRG before the autobaud process begins. To do this, first set
the GSMR with the ATB=0 and enable the BRG Rx clock to the
highest frequency. Immediately prior to the start of the autobaud
process (after device initialization) set the ATB bit equal to a
one.
7.9.2 BRG Configuration Register (BRGC)
Each BRGC is a 24-bit, memory-mapped, read/write register that is cleared at reset. A reset
disables the BRG and puts the BRGO output clock to the high level. The BRGC can be writ-
ten at any time with no need to disable the SCCs or the external devices that are connected
to the BRGO output clock. The BRG changes will occur at the end of the next BRG clock
cycle (no spikes will occur on the BRGO output clock). The BRGC allows on-the-fly
changes. Two on-the-fly changes to the BRG should not occur within a time shorter than the
period of at least two BRG input clocks.
Bits 23–18—Reserved
23
22
21
20
19
18
17
16
15
14
13
12
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RST
EN
EXTC1–EXTC0
ATB
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Freescale Semiconductor, Inc.
For More Information On This Product,
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