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| 型号： | MC68HC05E1MP |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| 封装： | PLASTIC, DIP-28 |
| 文件页数： | 39/86页 |
| 文件大小： | 709K |
| 代理商： | MC68HC05E1MP |
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General Release Specication
MC68HC05E1 — Revision 2.0
44
CPU Core
MOTOROLA
CPU Core
Figure 3-2. STOP/WAIT Flowcharts
3.7.2 Software Interrupt (SWI)
The SWI is an executable instruction and a non-maskable interrupt: it is
executed regardless of the state of the I bit in the CCR. If the I bit is zero
(interrupts enabled), SWI executes after interrupts which were pending
when the SWI was fetched, but before interrupts generated after the SWI
was fetched. The interrupt service routine address is specified by the
contents of memory locations $1FFC and $1FFD.
Turn On Oscillator
Wait for Time
Delay to Stabilize
1. Fetch
Reset
Vector or
2. Service
Interrupt
a. Stack
b. Set I Bit
c. Vector to
Interrupt
Routine
Restart
Processor Clock
1. Fetch
Reset
Vector or
2. Service
Interrupt
a. Stack
b. Set I Bit
c. Vector to
Interrupt
Routine
Y
N
STOP
WAIT
External
Interrupt
(IRQ)
Reset
Oscillator Active
Timer Clock Active
Processor Clocks
Stopped
Stop Oscillator
And All Clocks
Clear I Bit
Timer
Internal
Interrupt
CPI
Internal
Interrupt
External
Interrupt
(IRQ)
Reset
N
Y
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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