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参数资料
| 型号： | MC68HC05J5ADWR2 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | SOIC-20 |
| 文件页数： | 67/106页 |
| 文件大小： | 1069K |
| 代理商： | MC68HC05J5ADWR2 |
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July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
16-BIT TIMER
MOTOROLA
REV 2.1
9-5
NOTE
To prevent interrupts from occurring between readings of the ACNTH and ACNTL,
set the I bit in the condition code register (CCR) before reading ACNTH and clear
the I bit after reading ACNTL.
9.3
INPUT CAPTURE REGISTERS
Figure 9-6. Timer Input Capture Block Diagram
The input capture function is a technique whereby an external signal (connected
to PB0/TCAP pin) is used to trigger the 16-bit timer counter. In this way it is possi-
ble to relate the timing of an external signal to the internal counter value, and
hence to elapsed time.
NOTE
Since the TCAP pin is shared with the PB0 I/O pin, changing the state of the PB0
DDR or Data Register can cause an unwanted TCAP interrupt. This can be
avoided by clearing the ICIE bit before changing the conguration of PB0, and
clearing any pending interrupts before enabling ICIE.
The signal on the TCAP pin is rst directed to a schmitt trigger or a voltage
comparator as shown in Figure 9-8. Setting the TCAPS bit to “1” will enable the
comparator and the VDD/2 reference voltage.
ICIE
ICH ($14)
16-BIT COUNTER
÷ 4
INTERNAL
(fOSC ÷ 2)
TIMER1 CONTROL REG.
TIMER1
REQUEST
INPUT CAPTURE (ICF)
RESET
CLOCK
INTERRUPT
ICL ($15)
ICF
TIMER1 STATUS REG.
$12
$13
INTERNAL
($FFFC)
DATA
READ
ICH
READ
ICL
LATCH
BUS
IEDG
EDGE
SELECT
& DETECT
LOGIC
IEDG
INTERNAL
DATA
BUS
SIGNAL
CONDITIONING
PB0/
TCAP
TCAPS
(bit7 at $02)
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相关代理商/技术参数 |
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| MC68HC05J5AJDW | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:8-bit microcontroller units |
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