- 您现在的位置：买卖IC网 > PDF目录80536 > MC68HC05J5ADWR2 (MOTOROLA INC) 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20 PDF资料下载
参数资料
| 型号： | MC68HC05J5ADWR2 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | SOIC-20 |
| 文件页数： | 70/106页 |
| 文件大小： | 1069K |
| 代理商： | MC68HC05J5ADWR2 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页当前第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页
GENERAL RELEASE SPECIFICATION
July 16, 1999
MOTOROLA
16-BIT TIMER
MC68HC05J5A
9-8
REV 2.1
Reading the ICH inhibits further captures until the ICL is also read. Reading the
ICL after reading the timer status register (T1SR) clears the ICF ag bit. does not
inhibit transfer of the free-running counter. There is no conict between reading
the ICL and transfers from the free-running timer counters. The input capture reg-
isters always contain the free-running timer counter value which corresponds to
the most recent input capture.
NOTE
To prevent interrupts from occurring between readings of the ICH and ICL, set the
I bit in the condition code register (CCR) before reading ICH and clear the I bit
after reading ICL.
9.4
TIMER1 CONTROL REGISTER (T1CR)
The timer control register is shown in Figure 9-11 performs the following func-
tions:
Enables input capture interrupts
Enables output compare interrupts
Enables timer overow interrupts
Control the active edge polarity of the TCAP signal on pin PB0/TCAP
Reset clears all the bits in the T1CR with the exception of the IEDG bit which is
unaffected.
ICIE - INPUT CAPTURE INTERRUPT ENABLE
This read/write bit enables interrupts caused by an active signal on the PB0/
TCAP pin. Reset clears the ICIE bit.
1 =
Input capture interrupts enabled.
0 =
Input capture interrupts disabled.
T1OIE - TIMER OVERFLOW INTERRUPT ENABLE
This read/write bit enables interrupts caused by a timer1 overow. Reset clears
the T1OIE bit.
1 =
Timer1 overow interrupts enabled.
0 =
Timer1 overow interrupts disabled.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
T1CR
R
ICIE
0
T1OIE
000
IEDG
0
$0012
W
reset:
000000
U
0
U = UNAFFECTED BY RESET
Figure 9-11. Timer Control Register (T1CR)
相关PDF资料 |
PDF描述 |
|---|---|
| MC68HC05K1VDWR3 | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDSO16 |
| MSU2958C25-006Q | 8-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP44 |
| MSU2958C25-010U | 8-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP44 |
| MSU2958C16-011U | 8-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP44 |
| MSU2958C16-031J | 8-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQCC44 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC68HC05J5AJDW | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:8-bit microcontroller units |
| MC68HC05J5AJP | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:8-bit microcontroller units |
| MC68HC05J5AP | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:8-bit microcontroller units |
| MC68HC05JJ6 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:General Release Specification Microcontrollers |
| MC68HC05JJ6CDW | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:General Release Specification Microcontrollers |
发布紧急采购，3分钟左右您将得到回复。