参数资料
型号: MC68HC05RC18FN
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44
封装: PLASTIC, LCC-44
文件页数: 110/126页
文件大小: 1180K
代理商: MC68HC05RC18FN
NON-DISCLOSURE
AGREEMENT
REQUIRED
Carrier Modulator Transmitter (CMT)
General Release Specification
MC68HC05RC18 Rev. 2.1
82
Carrier Modulator Transmitter (CMT)
Freescale Semiconductor
EOC — End Of Cycle Status Flag
1 = End of modulator cycle (counter = SBUFF) has occurred
0 = Current modulation cycle in progress
EOC is set when a match occurs between the contents of the space
period register, SREG, and the down counter. This is recognized as
the end of the modulation cycle. At this time, the counter is initialized
with the (possibly new) contents of the mark period buffer, MBUFF,
and the space period register, SREG, is loaded with the (possibly new)
contents of the space period buffer, SBUFF. This flag is cleared by a
read of the MCSR followed by an access of MDR2 or MDR3. The EOC
flag is cleared by reset.
DIV2 — Divide-by-two prescaler
1 = Divide-by-two prescaler enabled
0 = Divide-by-two prescaler disabled
The divide-by-two prescaler causes the CMT to be clocked at the bus
rate when enabled and 2 x the bus rate when disabled (fosc). Since this
bit is not double buffered, it should not be set during a transmission.
EIMSK — External Interrupt Mask
1 = IRQ and keyscan interrupts masked
0 = IRQ and keyscan interrupts enabled
The external interrupt mask bit is used to mask IRQ and keyscan
interrupts. This bit is cleared by reset.
EXSPC — Extended Space Enable
1 = Extended space enabled
0 = Extended space disabled
For a description of the extended space enable bit, see 9.5.3
Extended Space Operation. This bit is cleared by reset.
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