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参数资料
型号： MC68HC05V7CFNR2
厂商： MOTOROLA INC
元件分类： 微控制器/微处理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC68
封装： PLASTIC, LCC-68
文件页数： 18/170页
文件大小： 589K
代理商： MC68HC05V7CFNR2
MOTOROLA
SECTION 15: MESSAGE DATA LINK CONTROLLER
Page 100
MC68HC05V7 Specification Rev. 1.0
The MDLC will attempt to receive every message that it sends, so the RXMS bit will usually
be set a short time after the TXMS bit is set.
Because these bits act independently, cannot be written to, and have separate clearing
mechanisms, it is not possible to inadvertently miss an interrupt.
15.2.3.4
Clearing Wake Up Interrupts
Although no flag bit is affected by the MDLC waking up from MDLC Stop Mode (entered by
’STOP’ or ’WAIT’ with WCM bit set previously) due to network activity, the CPU interrupt
request that is generated by the wake up is cleared by an access of the MRSR register.
15.2.4
MDLC TX CONTROL REGISTER (MTCR) $10
This register controls the operation of the MDLC transmitter, including the Tx Buffer.
All bits may be read in all modes of MCU operation.
Bits 4, 5, 6, and 7 will always read as zeros and can never be written to.
Bits 0, 1, 2, and 3 can be written to in all modes of MCU operation.
15.2.4.1
TC0,1,2,3 - Transmit Count
These bits determine the length of the message body (not including the CRC byte) to be
sent. Internally, they are reset to $00 following a reset.
The programmer should first determine that the MDLC is ready to transmit, then load the
message header and data bytes into the Tx Buffer, and finally write the length of the body
of the message (excluding CRC byte) into this register.
This will cause the MDLC to initiate transmission of the contents of the Tx Buffer according
to the J1850 protocol. Once the last byte has been sent, a Cyclic Redundancy Check
(CRC) byte will automatically be appended to the end of the message body.
Once the CRC has been successfully sent, a CPU interrupt request will be generated (if the
Interrupt Enable (IE) bit is set) and the Tx Message Successful (TXMS) bit will be set in the
MSR register.
An access of this register will clear the CPU interrupt request and the TXMS bit.
The valid range of values that may be written to this register is $01 to $0B. Since the Tx
Buffer is 11 bytes long, any value greater than or equal to $0C written to this register will
create a Tx Buffer overflow error and cause the MDLC to not transmit that message.
Figure 15-5:
MDLC Tx Control Register (MTCR)
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
TC1
TC0
TC2
TC3
0
RESET
00000000
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