
System Integration Module (SIM)
MC68HC08GR32A MC68HC08GR16A Data Sheet, Rev. 0
168
Freescale Semiconductor
14.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in
Figure 14-4. This clock
originates from either an external oscillator or from the on-chip PLL.
14.2.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four
or the PLL output (CGMVCLK) divided by four.
14.2.2 Clock Startup from POR or LVI Reset
When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the
CPU and peripherals are inactive and held in an inactive phase until after the 4096 CGMXCLK cycle POR
timeout has completed. The RST pin is driven low by the SIM during this entire period. The bus clocks
start upon completion of the timeout.
14.2.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt or reset, the SIM allows CGMXCLK to clock the SIM counter.
The CPU and peripheral clocks do not become active until after the stop delay timeout. This timeout is
In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules.
Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
$FE03
Break Flag Control Register
(SBFCR)
Read:
BCFE
RRRRRRR
Write:
Reset:
0
$FE04
Interrupt Status Register 1
(INT1)
Read:
IF6
IF5
IF4
IF3
IF2
IF1
0
Write:
RRRRRRRR
Reset:
00000000
$FE05
Interrupt Status Register 2
(INT2)
Read:
IF14
IF13
IF12
IF11
IF10
IF9
IF8
IF7
Write:
RRRRRRRR
Reset:
00000000
$FE06
Interrupt Status Register 3
(INT3)
Read:
0
IF20
IF19
IF18
IF17
IF16
IF15
Write:
RRRRRRRR
Reset:
00000000
Addr.
Register Name
Bit 7
654321
Bit 0
= Unimplemented
R
= Reserved
Figure 14-3. SIM I/O Register Summary (Continued)