参数资料
型号: MC68HC11A1VP2
厂商: ABILIS SYSTEMS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP48
封装: PLASTIC, DIP-48
文件页数: 38/158页
文件大小: 3803K
代理商: MC68HC11A1VP2
ELECTRICAL CHARACTERISTICS
MC68HC11A8
A-12
TECHNICAL DATA
A
NOTES:
1. If this setup time is met, STRB acknowledges in the next cycle. If it is not met, the response may be delayed one
more cycle.
2. Port C and D timing is valid for active drive (CWOM and DWOM bits not set in PIOC and SPCR registers respec-
tively).
3. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.
Table A-5 Peripheral Port Timing
VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH
Characteristic
Symbol
1.0 MHz
2.0 MHz
3.0 MHz
Unit
Min
Max
Min
Max
Min
Max
Frequency of Operation (E-Clock Frequency)
fo
dc
1.0
dc
2.0
dc
3.0
MHz
E-Clock Period
tcyc
1000
500
333
ns
Peripheral Data Setup Time
(MCU Read of Ports A, C, D, and E)
tPDSU
100
100
100
ns
Peripheral Data Hold Time
(MCU Read of Ports A, C, D, and E)
tPDH
50—50—50—
ns
Delay Time, Peripheral Data Write
MCU Write to Port A
MCU Writes to Ports B, C, and D
tPWD = 1/4 tcyc + 100 ns
tPWD
200
350
200
225
200
183
ns
Input Data Setup Time (Port C)
tIS
60—60—60—
ns
Input Data Hold Time (Port C)
tIH
100
100
100
ns
Delay Time, E Fall to STRB tDEB = 1/4 tcyc + 100 ns
tDEB
350
225
183
ns
Setup Time, STRA Asserted to E Fall (Note 1)
tAES
0—0—0—ns
Delay Time, STRA Asserted to Port C Data Output Valid
tPCD
100
100
100
ns
Hold Time, STRA Negated to Port C Data
tPCH
10—10—10—
ns
Three-State Hold Time
tPCZ
150
150
150
ns
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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