参数资料
型号: MC68HC11D3CFB
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, 2 MHz, MICROCONTROLLER, PQFP44
封装: QFP-44
文件页数: 109/131页
文件大小: 1640K
代理商: MC68HC11D3CFB
MC68HC11D3
SERIAL PERIPHERAL INTERFACE
MOTOROLA
TECHNICAL DATA
8-1
SECTION 8
SERIAL PERIPHERAL INTERFACE
The serial peripheral interface (SPI), an independent serial communications sub-
system, allows the MCU to communicate synchronously with peripheral devices, such
as transistor-transistor logic (TTL) shift registers, liquid crystal diode (LCD) display
drivers, analog-to-digital converter subsystems, and other microprocessors. The SPI
is also capable of inter-processor communication in a multiple master system. The SPI
system can be configured as either a master or a slave device with data rates as high
as one half of the E-clock rate when configured as master, and as fast as the E-clock
rate when configured as slave.
8.1 Functional Description
The central element in the SPI system is the block containing the shift register and the
read data buffer. The system is single buffered in the transmit direction and double
buffered in the receive direction. This means that new data for transmission cannot be
written to the shifter until the previous transfer is complete; however, received data is
transferred into a parallel read data buffer so the shifter is free to accept a second se-
rial character. As long as the first character is read out of the read data buffer before
the next serial character is ready to be transferred, no overrun condition occurs. A sin-
gle MCU register address is used for reading data from the read data buffer, and for
writing data to the shifter.
The SPI status block represents the SPI status functions (transfer complete, write col-
lision, and mode fault) performed by the serial peripheral status register (SPSR). The
SPI control block represents those functions that control the SPI system through the
serial peripheral control register (SPCR).
Refer to Figure 8-1, which shows the SPI block diagram.
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