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参数资料
型号： MC68HC11F1VPU3
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 8-BIT, EEPROM, 3 MHz, MICROCONTROLLER, PQFP80
封装： 14 X 14 MM, 1.40 MM HEIGHT, LQFP-80
文件页数： 34/162页
文件大小： 4554K
代理商： MC68HC11F1VPU3
ANALOG-TO-DIGITAL CONVERTER
MOTOROLA
TECHNICAL DATA
10-5
10.2 A/D Converter Power-Up and Clock Select
Bit 7 of the OPTION register controls A/D converter power up. Clearing ADPU re-
moves power from and disables the A/D converter system. Setting ADPU enables the
A/D converter system. Stabilization of the analog bias voltages requires a delay of as
much as 100
s after turning on the A/D converter. When the A/D converter system is
operating with the MCU E clock, all switching and comparator operations are synchro-
nized to the MCU clocks. This allows the comparator results to be sampled at quiet
times, which minimizes noise errors. The internal RC oscillator is asynchronous to the
MCU clock, so noise affects A/D converter results, which lowers accuracy slightly
while CSEL = 1.
*Can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes
ADPU — A/D Power-Up
0 = A/D powered down
1 = A/D powered up
CSEL — Clock Select
0 = A/D and EEPROM use system E clock
1 = A/D and EEPROM use internal RC clock
IRQE — Configure IRQ for Edge-Sensitive Only Operation
Refer to SECTION 5 RESETS AND INTERRUPTS.
DLY — Enable Oscillator Start-up Delay
Refer to SECTION 5 RESETS AND INTERRUPTS.
CME — Clock Monitor Enable
Refer to SECTION 5 RESETS AND INTERRUPTS.
FCME — Force Clock Monitor Enable
Refer to SECTION 5 RESETS AND INTERRUPTS.
CR[1:0] — COP Timer Rate Select Bits
Refer to SECTION 5 RESETS AND INTERRUPTS and SECTION 9 TIMING SYS-
TEM.
10.3 Conversion Process
The A/D conversion sequence begins one E-clock cycle after a write to the A/D control/
status register, ADCTL. The bits in ADCTL select the channel and the mode of con-
version.
An input voltage equal to VRL converts to $00 and an input voltage equal to VRH con-
verts to $FF (full scale), with no overflow indication. For ratiometric conversions of this
type, the source of each analog input should use VRH as the supply voltage and be
referenced to VRL.
OPTION — System Configuration Options
$1039
Bit 7
654321
Bit 0
ADPU
CSEL
IRQE*
DLY*
CME
FCME*
CR1*
CR0*
RESET:
0001000
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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