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参数资料
型号： MC68HC11F1VPU4
厂商： MOTOROLA INC
元件分类： 微控制器/微处理器
英文描述： Technical Summary 8-Bit Microcontroller
中文描述： 8-BIT, EEPROM, 4 MHz, MICROCONTROLLER, PQFP80
封装： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-80
文件页数： 80/163页
文件大小： 711K
代理商： MC68HC11F1VPU4
MC68HC11F1
PIN DESCRIPTIONS
MOTOROLA
TECHNICAL DATA
2-9
OR mode, (PORTD bits are at logic level zero), pins are actively driven low by the N-
channel driver. When a port D bit is at logic level one, the associated pin is in a high-
impedance state, as neither the N-channel nor the P-channel devices are active. It is
customary to have an external pull-up resistor on lines that are driven by open-drain
devices. Port D can be configured for wired-OR operation in any operating mode.
Refer to SECTION 6 PARALLEL INPUT/OUTPUT, SECTION 7 SERIAL COMMUNI-
CATIONS INTERFACE, and SECTION 8 SERIAL PERIPHERAL INTERFACE.
2.11.5 Port E
Port E is an 8-bit input-only port that is also used as the analog input port for the ana-
log-to-digital converter. Port E pins that are not used for the A/D system can be used
as general-purpose inputs. However, PORTE should not be read during the sample
portion of an A/D conversion sequence.
Refer to SECTION 10 ANALOG-TO-DIGITAL CONVERTER.
2.11.6 Port F
Port F is an 8-bit output-only port. In single-chip mode, port F pins are general-purpose
output pins (PF[7:0]). In expanded mode, port F pins act as the low-order address out-
puts (ADDR[7:0]).
PORTF can be read at any time. Reads of PORTF return the pin driver input level. If
PORTF is written, the data is stored in internal latches. It drives the pins only in single-
chip or bootstrap mode. In expanded operating modes, port F pins are the low-order
address outputs (ADDR[7:0]).
Refer to SECTION 6 PARALLEL INPUT/OUTPUT.
2.11.7 Port G
Port G is an 8-bit general-purpose I/O port. When enabled, four chip select signals are
alternate functions of port G bits [7:4].
PORTG can be read at any time. Inputs return the pin level; outputs return the pin driv-
er input level. If PORTG is written, the data is stored in internal latches. It drives the
pins only if they are configured as outputs.
The GWOM control bit in the OPT2 register disables port G's P-channel output drivers.
Because the N-channel driver is not affected by GWOM, setting GWOM causes port
G to become an open-drain-type output port suitable for wired-OR operation. In wired-
OR mode, (PORTG bits are at logic level zero), pins are actively driven low by the N-
channel driver. When a port G bit is at logic level one, the associated pin is in a high-
impedance state, as neither the N-channel nor the P-channel devices are active. It is
customary to have an external pull-up resistor on lines that are driven by open-drain
devices. Port G can be configured for wired-OR operation in any operating mode.
Refer to SECTION 6 PARALLEL INPUT/OUTPUT and SECTION 4 OPERATING
MODES AND ON-CHIP MEMORY.
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