参数资料
型号: MC68HC705J1ACP
厂商: Freescale Semiconductor
文件页数: 116/162页
文件大小: 0K
描述: IC MCU 4MHZ 1.2K OTP 20-DIP
标准包装: 18
系列: HC05
核心处理器: HC05
芯体尺寸: 8-位
速度: 4MHz
外围设备: POR,WDT
输入/输出数: 14
程序存储器容量: 1.2KB(1.2K x 8)
程序存储器类型: OTP
RAM 容量: 64 x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 20-DIP(0.300",7.62mm)
包装: 管件
Central Processor Unit (CPU)
Instruction Set
MC68HC705J1A — Rev. 4.0
Technical Data
Central Processor Unit (CPU)
3.6.2.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
NOTE:
Do not use BRCLR or BRSET instructions on registers with write-only
bits.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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