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| 型号： | MC68HC705JB2DW |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | SOIC-20 |
| 文件页数： | 58/128页 |
| 文件大小： | 2493K |
| 代理商： | MC68HC705JB2DW |
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August 28, 1998
GENERAL RELEASE SPECIFICATION
INTERRUPTS
REV 1.1
4-5
The IRQ pin is one source of an IRQ interrupt and a mask option can also enable
the four lower Port A pins (PA0 thru PA3) to act as other IRQ interrupt sources.
Refer to Figure 4-2 for the following descriptions. IRQ interrupt source comes
from IRQ latch. The IRQ latch will be set on the falling edge of the IRQ pin or on
any rising edge of PA0-3 pins if PA0-3 interrupts have been enabled. If "edge-only"
sensitivity is chosen by a mask option, only the IRQ latch output can activate an
IRQF ag which creates a request to the CPU to generate the IRQ interrupt
sequence. This makes the IRQ interrupt sensitive to the following cases:
Falling edge on the IRQ pin.
Rising edge on any PA0-PA3 pin with IRQ enabled (via mask option).
If level sensitivity is chosen, the active high state the signal to the clock input of
the IRQ latch can also activate an IRQF ag which creates an IRQ request to the
CPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt
sensitive to the following cases:
Low level on the IRQ pin.
Falling edge on the IRQ pin.
High level on any PA0- PA3 pin with IRQ enabled (via mask option).
Rising edge on any PA0- PA3 pin with IRQ enabled (via mask option).
The IRQE enable bit controls whether an active IRQF ag can generate an IRQ
interrupt sequence. This interrupt is serviced by the interrupt service routine
located at the address specied by the contents of $1FFA and $1FFB.
The IRQ latch is automatically cleared by entering the interrupt service routine IF
IRQE enable bit is cleared. If IRQE enable bit is also set, the only way of clearing
IRQF is by writing a logic one to the IRQR acknowledge bit. Writing a logic one to
the IRQR acknowledge bit in the ICSR is the other way of clearing IRQF ag. As
long as the output state of the IRQF ag bit is active the CPU will continuously re-
enter the IRQ interrupt sequence until the active state is removed or the IRQE
enable bit is cleared.
4.4.2 IRQ Control/status Register (ICSR) $0A
The IRQ interrupt function is controlled by the ICSR located at $000A. All unused
bits in the ICSR will read as logic zeros. The IRQF bit is cleared and IRQE bit is
set by reset.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ICSR
R
IRQE
0
IRQF
0
$000A
W
IRQR
reset:
10000000
Figure 4-3. IRQ Control and Status Register (ICSR)
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| MC68HC705JB4DW | 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
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| MC68HC705JP7CDW | 功能描述:IC MCU 8BIT 28-SOIC RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 其它有关文件:STM32F101T8 View All Specifications 特色产品:STM32 32-bit Cortex MCUs 标准包装:490 系列:STM32 F1 核心处理器:ARM? Cortex?-M3 芯体尺寸:32-位 速度:36MHz 连通性:I²C，IrDA，LIN，SPI，UART/USART 外围设备:DMA，PDR，POR，PVD，PWM，温度传感器，WDT 输入/输出数:26 程序存储器容量:64KB（64K x 8） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:10K x 8 电压 - 电源 (Vcc/Vdd):2 V ~ 3.6 V 数据转换器:A/D 10x12b 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:36-VFQFN，36-VFQFPN 包装:托盘 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名称:497-9032STM32F101T8U6-ND |
| MC68HC705JP7CP | 制造商:Rochester Electronics LLC 功能描述: 制造商:Freescale Semiconductor 功能描述: |
| MC68HC705K1CDW | 制造商:Motorola Inc 功能描述: |
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