参数资料
型号: MC68HC705JB2DW
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDSO20
封装: SOIC-20
文件页数: 64/128页
文件大小: 2493K
代理商: MC68HC705JB2DW
GENERAL RELEASE SPECIFICATION
August 28, 1998
RESETS
MC68HC705JB2
5-2
REV 1.1
5.1
EXTERNAL RESET (RESET)
The RESET pin is the only external source of a reset. This pin is connected to a
Schmitt trigger input gate to provide an upper and lower threshold voltage
separated by a minimum amount of hysteresis. This external reset occurs
whenever the RESET pin is pulled below the lower threshold and remains in reset
until the RESET pin rises above the upper threshold. This active low input will
generate the RST signal and reset the CPU and peripherals. This pin is also an
output pin whenever the LVR triggers an internal reset. Termination of the external
RESET input or the USB reset or LVR are the only reset sources that can alter the
operating mode of the MCU.
NOTE
Activation of the RST signal is generally referred to as reset of the
device, unless otherwise specied.
5.2
INTERNAL RESETS
The four internally generated resets are the initial power-on reset function, the
USB reset ag reset, the illegal address detector reset and the low voltage reset
(LVR). Termination of the external RESET input or LVR or USB reset or ILADR are
the reset sources that can alter the operating mode of the MCU. The other internal
resets will not have any effect on the mode of operation when their reset state
ends.
5.2.1 Power-On Reset (POR)
The internal POR is generated on power-up to allow the clock oscillator to
stabilize. The POR is strictly for power turn-on conditions and is not able to detect
a drop in the power supply voltage (brown-out). There is an oscillator stabilization
delay of 128 or 4064 internal processor bus clock cycles (PH2) for Ceramic
Resonator or Crystal after the oscillator becomes active.
The POR will generate the RST signal which will reset the CPU. If any other reset
function is active at the end of this 128 or 4064 cycle delay, the RST signal will
remain in the reset condition until the other reset condition(s) end.
5.2.2 USB Reset
The USB reset is generated by a detection on the USB bus reset signal. For
MC68HC705JB2, seeing a single-end zero on its upstream port for 4 to 8 bit times
will set RSTF bit in UIR0 register. The detections will also generate the RST signal
to reset the CPU and other peripherals in the MCU.
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相关PDF资料
PDF描述
MC68HC705JB2P 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP20
MC68HC705JB4P 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP28
MC68HC705K1CDW 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDSO16
MC68HC705K1CP 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDIP16
MC68HC705K1S 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, CDIP16
相关代理商/技术参数
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