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参数资料
型号： MC68HC705JJ7CP
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP20
封装： PLASTIC, DIP-20
文件页数： 114/164页
文件大小： 1165K
代理商： MC68HC705JJ7CP
Low-Power Modes
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
53
6.3.2 Wait Mode
The WAIT instruction puts the MCU in a low-power wait mode which consumes more power than the stop
mode and affects the MCU as follows:
Enables interrupts by clearing the I bit in the condition code register
Enables external interrupts by setting the IRQE bit in the IRQ status and control register
Stops the CPU clock which drives the address and data buses, but allows the selected oscillator
to continue to clock the core timer, programmable timer, analog subsystem, and SIOP
The WAIT instruction does not affect any other bits, registers, or I/O lines.
These conditions restart the CPU bus clock and bring the MCU out of wait mode:
An external interrupt signal on the IRQ/VPP pin — A high-to-low transition on the IRQ/VPP pin loads
the program counter with the contents of locations $1FFA and $1FFB.
An external interrupt signal on a port A external interrupt pin — If selected by PIRQ bit in the MOR,
a low-to-high transition on a PA3–PA0 pin loads the program counter with the contents of locations
$1FFA and $1FFB.
A core timer interrupt — A core timer overflow or a real-time interrupt loads the program counter
with the contents of locations $1FF8 and $1FF9.
A programmable timer interrupt — A programmable timer interrupt driven by an input capture,
output compare, or timer overflow loads the program counter with the contents of locations $1FF6
and $1FF7.
An SIOP interrupt — An SIOP interrupt driven by the completion of transmitted or received 8-bit
data loads the program counter with the contents of locations $1FF4 and $1FF5.
An analog subsystem interrupt — An analog subsystem interrupt driven by a voltage comparison
loads the program counter with the contents of locations $1FF2 and $1FF3.
A COP watchdog reset — A timeout of the COP watchdog resets the MCU and loads the program
counter with the contents of locations $1FFE and $1FFF. Software can enable real-time interrupts
so that the MCU can periodically exit the wait mode to reset the COP watchdog.
An external reset — A logic 0 on the RESET pin resets the MCU and loads the program counter
with the contents of locations $1FFE and $1FFF.
When the MCU exits the wait mode, there is no delay before code executes like occurs when exiting the
stop or halt modes.
6.3.3 Halt Mode
The STOP instruction puts the MCU in halt mode if selected by the SWAIT bit in the MOR. Halt mode is
identical to wait mode, except that a variable recovery delay occurs when the MCU exits halt mode. A
recovery time of from 1 to 16 or from 1 to 4064 internal bus cycles can be selected by the DELAY bit in
the MOR.
If the SWAIT bit is set in the MOR to put the MCU in halt mode, the COP watchdog cannot be turned off
inadvertently by a STOP instruction.
相关PDF资料
PDF描述
MC68HC705JJ7S 8-BIT, UVPROM, 2.1 MHz, MICROCONTROLLER, CDIP20
MC68HC705K1DWR2 8-BIT, OTPROM, MICROCONTROLLER, PDSO16
MC68HC705K1CP 8-BIT, OTPROM, MICROCONTROLLER, PDIP16
MC68HC705K1P 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDIP16
MC68HC705K1DW 8-BIT, OTPROM, MICROCONTROLLER, PDSO16
相关代理商/技术参数
参数描述
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MC68HC705JP7CP 制造商:Rochester Electronics LLC 功能描述: 制造商:Freescale Semiconductor 功能描述:
MC68HC705K1CDW 制造商:Motorola Inc 功能描述:
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