参数资料
型号: MC68HC705P6ACDW
厂商: Freescale Semiconductor
文件页数: 47/98页
文件大小: 0K
描述: IC MCU 2.1MHZ 4.5K OTP 28-SOIC
标准包装: 26
系列: HC05
核心处理器: HC05
芯体尺寸: 8-位
速度: 2.1MHz
连通性: SIO
外围设备: POR,WDT
输入/输出数: 21
程序存储器容量: 4.5KB(4.5K x 8)
程序存储器类型: OTP
RAM 容量: 176 x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
数据转换器: A/D 4x8b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
包装: 管件
Timer During Wait/Halt Mode
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
51
To prevent OCF from being set between the time it is read and the time the output compare registers are
updated, use this procedure:
1.
Disable interrupts by setting the I bit in the condition code register.
2.
Write to OCRH. Compares are now inhibited until OCRL is written.
3.
Clear bit OCF by reading timer status register (TSR).
4.
Enable the output compare function by writing to OCRL.
5.
Enable interrupts by clearing the I bit in the condition code register.
8.4 Timer During Wait/Halt Mode
The CPU clock halts during the wait (or halt) mode, but the timer remains active. If interrupts are enabled,
a timer interrupt will cause the processor to exit the wait mode.
8.5 Timer During Stop Mode
In the stop mode, the timer stops counting and holds the last count value if STOP is exited by an interrupt.
If STOP is exited by RESET, the counters are forced to $FFFC. During STOP, if at least one valid input
capture edge occurs at the TCAP pins, the input capture detect circuit is armed. This does not set any
timer flags or wake up the MCU, but if an interrupt is used to exit stop mode, there is an active input
capture flag and data from the first valid edge that occurred during the stop mode. If reset is used to exit
stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred.
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