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型号： MC68HC711D3CFN2
厂商： Freescale Semiconductor
文件页数： 45/124页
文件大小： 0K
描述： IC MCU 2MHZ 4K OTP 44-PLCC
标准包装： 26
系列： HC11
核心处理器： HC11
芯体尺寸： 8-位
速度： 2MHz
连通性： SCI，SPI
外围设备： POR，WDT
输入/输出数： 26
程序存储器容量： 4KB（4K x 8）
程序存储器类型： OTP
RAM 容量： 192 x 8
电压 - 电源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 44-LCC（J 形引线）
包装： 管件
CENTRAL PROCESSING UNIT
TECHNICAL DATA
3-7
to proceed. The effective address can be specified within an instruction, or it can be
calculated.
3.4.1 Immediate
In the immediate addressing mode an argument is contained in the byte(s) immediate-
ly following the opcode. The number of bytes following the opcode matches the size
of the register or memory location being operated on. There are two-, three-, and four-
(if prebyte is required) byte immediate instructions. The effective address is the ad-
dress of the byte following the instruction.
3.4.2 Direct
In the direct addressing mode, the low-order byte of the operand address is contained
in a single byte following the opcode, and the high-order byte of the address is as-
sumed to be $00. Addresses $00–$FF are thus accessed directly, using two-byte in-
structions. Execution time is reduced by eliminating the additional memory access
required for the high-order address byte. In most applications, this 256-byte area is re-
served for frequently referenced data. In M68HC11 MCUs, the memory map can be
configured for combinations of internal registers, RAM or external memory to occupy
these addresses.
3.4.2.1 Extended
In the extended addressing mode, the effective address of the argument is contained
in two bytes following the opcode byte. These are three-byte instructions (or four-byte
instructions if a prebyte is required). One or two bytes are needed for the opcode and
two for the effective address.
3.4.2.2 Indexed
In the indexed addressing mode, an 8-bit unsigned offset contained in the instruction
is added to the value contained in an index register (IX or IY) — the sum is the effective
address. This addressing mode allows referencing any memory location in the 64
Kbyte address space. These are from two- to five-byte instructions, depending on
whether or not a prebyte is required.
3.4.2.3 Inherent
In the inherent addressing mode, all the information necessary to execute the instruc-
tion is contained in the opcode. Operations that use only the index registers or accu-
mulators, as well as control instructions with no arguments, are included in this
addressing mode. These are one- or two-byte instructions.
3.4.2.4 Relative
The relative addressing mode is used only for branch instructions. If the branch con-
dition is true, an 8-bit signed offset included in the instruction is added to the contents
of the program counter to form the effective branch address. Otherwise, control pro-
ceeds to the next instruction. These are usually two-byte instructions.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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