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参数资料
| 型号： | MC68HC711EA9CFS2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, UVPROM, 2 MHz, MICROCONTROLLER, CQCC52 |
| 封装： | WINDOWED, CERAMIC, LCC-52 |
| 文件页数： | 32/58页 |
| 文件大小： | 583K |
| 代理商： | MC68HC711EA9CFS2 |
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MOTOROLA
MC68HC11EA9
38
MC68HC11EA9TS/D
OC1I–OC4I — Output Compare (OCx) Interrupt Enable
If the OCxI enable bit is set when a match occurs, an interrupt is generated.
0 = Interrupts from OCx channel disabled
1 = Successful compares on OCx channel generate interrupts
I4/O5I — Input Capture 4/Output Compare 5 Interrupt Enable
When I4/O5 in PACTL is one, I4/O5I is the input capture 4 interrupt enable bit and edges on the I4/O5
pin generate interrupts. When I4/O5 in PACTL is zero, I4/O5I is the output compare 5 interrupt enable
bit and successful matches generate interrupts.
0 = Interrupts from IC4/OC5 channel disabled
1 = Interrupts from IC4/OC5 channel enabled
IC1I–IC3I — Input Capture (ICx) Interrupt Enable
If the ICxI enable bit is set when an edge is detected on the ICx pin, an interrupt is generated.
0 = Interrupts from ICx channel disabled
1 = Edges detected on ICx pin generate interrupts
NOTE
Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones in TMSK1 enable
the corresponding interrupt sources.
Clear a flag by writing a one to the appropriate bit.
OC1F–OC4F — Output Compare (OCx) Interrupt Flag
If the OCxI enable bit is set when a match occurs, the corresponding flag bit is set and an interrupt is
generated.
0 = No match has occurred
1 = A successful compare has occurred on OCx channel
I4/O5I — Input Capture 4/Output Compare 5 Interrupt Enable
When I4/O5 in PACTL is one, I4/O5I is the input capture 4 interrupt enable bit and edges (rising or fall-
ing, depending on configuration) on the I4/O5 pin cause this flag to be set and an interrupt is generated.
When I4/O5 in PACTL is zero, I4/O5I is the output compare 5 interrupt enable bit and successful match-
es cause this flag to be set and an interrupt generated.
0 = Interrupts from IC4/OC5 channel disabled
1 = Interrupts from IC4/OC5 channel enabled
IC1I–IC3I — Input Capture (ICx) Interrupt Enable
If the ICxI enable bit is set when an edge (rising or falling, depending on configuration) is detected on
the ICx pin, an interrupt is generated.
0 = Interrupts from ICx channel disabled
1 = Edges detected on ICx pin generate interrupts
TMSK1 — Timer Interrupt Mask 1
$1022
BIT 7
654321
BIT 0
OC1I
OC2I
OC3I
OC4I
I4/O5I
IC1I
IC2I
IC3I
RESET:
00000000
TFLG1 — Timer Interrupt Flag 1
$1023
BIT 7
654321
BIT 0
OC1F
OC2F
OC3F
OC4F
I4/O5F
IC1F
IC2F
IC3F
RESET:
00000000
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For More Information On This Product,
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