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| 型号： | MC68HC711EA9CP3 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP56 |
| 封装： | PLASTIC, SDIP-56 |
| 文件页数： | 21/58页 |
| 文件大小： | 583K |
| 代理商： | MC68HC711EA9CP3 |
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MOTOROLA
MC68HC11EA9
28
MC68HC11EA9TS/D
Table 11 Strobed and Handshake Parallel I/O Control Bit Summary
Port pin function is mode dependent. Do not confuse pin function with the electrical state of the pin at
reset. Port pins are either driven to a specified logic level or are configured as high impedance inputs.
I/O pins configured as high-impedance inputs have port data that is indeterminate. The contents of the
corresponding latches are dependent upon the electrical state of the pins during reset. In port descrip-
tions, an "I" indicates this condition. Port pins that are driven to a known logic level during reset are
shown with a value of either one or zero. Some control bits are unaffected by reset. Reset states for
these bits are indicated with a "U".
NOTE
The timer forces the I/O state to output for each port A line associated with an en-
abled output compare. In these cases the data direction bits will not be changed,
but have no effect on these lines. The DDRA will revert to controlling data direction
when the associated timer compare is disabled. Input captures do not force either
the I/O state of the pin or the state of DDRA. To enable PA3 as fourth input capture,
set the I4/O5 bit in the PACTL register. Otherwise, PA3 is configured as a fifth out-
put compare out of reset, with bit I4/O5 being cleared. If the DDA3 bit in DDRA is
set (configuring PA3 as an output), and IC4 is enabled, writes to PA3 cause edges
on the pin to result in input captures. Writing to TI4/O5 has no effect when the TI4/
O5 register is acting as IC4. PA7 drives the pulse accumulator input but also can
be configured for general-purpose I/O or output compare. DDA7 bit in DDRA reg-
ister configures PA7 for either input or output. Note that even when PA7 is config-
ured as an output, the pin still drives the pulse accumulator input.
PORTA — Port A Data
$1000
BIT 7
654321
BIT 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
RESET:
IIIIIIII
Alt. Pin
Func.:
PAI
OC2
OC3
OC4
IC4/OC5
IC1
IC2
IC3
And/or
OC1
—
1
0
1
0
1
Port C
Driven
STRA
Active Edge
Follow
DDRC
Follow
DDRC
Simple
strobed
mode
Full
input
handshake
mode
Full
output
handshake
mode
0
1
X
0
1
X
0 = STRB
active level
Read PIOC
with STAF = 1
then read
PORTCL
Read PIOC
with STAF = 1
then read
PORTCL
Read PIOC
with STAF = 1
then write
PORTCL
1 = STRB
active pulse
0 = STRB
active level
1 = STRB
active pulse
STAF
Clearing
Sequence
HNDS OIN
PLS
EGA
Inputs latched
into PORTCL
on any
active edge
on STRA
Driven as outputs if
STRA at active
level; follows
DDRC if STRA not
at active level
STRB pulses
on writes to
PORTB
Normal output
port, unaffected
in handshake
modes
Normal output
port, unaffected
in handshake
modes
Port C
Port B
Inputs latched
into PORTCL
on any
active edge
on STRA
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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