
Technical Data
MC68HC705C4A MC68HSC705C4A — Rev. 3.0
56
Interrupts
MOTOROLA
Interrupts
Port B external interrupt pins can be falling-edge sensitive only or both
falling-edge and low-level sensitive, depending on the state of the IRQ
bit in the option register at location $1FDF.
When the IRQ bit is a logic 1, a falling edge or a low level on a port B
external interrupt pin latches an external interrupt request. As long as
any port B external interrupt pin is low, an external interrupt request is
present, and the CPU continues to execute the interrupt service routine.
When the IRQ bit is a logic 0, a falling-edge only on a port B external
interrupt pin latches an external interrupt request. A subsequent port B
external interrupt request can be latched only after the voltage level of
the previous port B external interrupt signal returns to a logic 1 and then
falls again to a logic 0.
Figure 4-3 shows the port B input/output (I/O) logic.
4.3.4 Capture/Compare Timer Interrupts
The capture/compare timer can generate these interrupts:
Input capture interrupt
Output compare interrupt
Timer overflow interrupt
Setting the I bit in the condition code register disables all interrupts
except for SWI and timer interrupts.
Input Capture Interrupt — The input capture flag bit (ICF)
indicates a transfer from the timer registers to the input capture
registers. ICF becomes set when an active edge occurs on the
TCAP pin. ICF generates an interrupt request if the input capture
interrupt enable bit (ICIE) is set also.
Output Compare Interrupt — The output compare flag bit (OCF)
indicates a transfer of the output level bit (OLVL) to the TCMP pin.
OCF becomes set when the 16-bit counter counts up to the value
programmed in the output compare registers. OCF generates an
interrupt request if the output compare interrupt enable bit (OCIE)
is set also.