参数资料
型号: MC68LNC705C9ACFN
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC44
封装: PLASTIC, LCC-44
文件页数: 140/177页
文件大小: 1941K
代理商: MC68LNC705C9ACFN
Resets
COP During Stop Mode
MC68HC705C9A — Rev. 4.0
Advance Information
MOTOROLA
Resets
65
In the event that an inadvertent STOP instruction is executed, neither
COP will allow the system to recover. The MC68HC705C9A offers two
solutions to this problem, one available in C9A mode (see 5.10.1 Clock
Monitor Reset) and one available in C12A mode (see 5.10.2 STOP
5.10.1 Clock Monitor Reset
When configured as a C9A, the clock monitor circuit can provide a
system reset if the clock stops for any reason, including stop mode.
When the CME bit in the C9A COP control register is set, the clock
monitor detects the absence of the internal bus clock for a certain period
of time. The timeout period is dependent on the processing parameters
and varies from 5
s to 100 s, which implies that systems using a bus
clock rate of 200 kHz or less should not use the clock monitor.
If a slow or absent clock is detected, the clock monitor causes a system
reset. The reset is issued to the external system via the bidirectional
RESET pin for four bus cycles if the clock is slow or until the clocks
recover in the case where the clocks are absent.
5.10.2 STOP Instruction Disable Option
On the ROM device MC68HC05C12A, stop mode can be disabled by
mask option. This causes the CPU to interpret the STOP instruction as
a NOP so the device will never enter stop mode; if the user code is not
being executed properly, the COP will provide a system reset.
To emulate this feature on the MC68HC705C9A (configured as an
MC68HC05C12A), set the STOPDIS bit in the C12MOR. Stop mode will
not actually be disabled as on the MC68HC05C12A, but the clock
monitor circuit will be activated. If the CPU executes a STOP instruction,
the clock monitor will provide a system reset.
NOTE:
This feature cannot be used with operating frequencies of 200 kHz or
less.
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