参数资料
型号: MC705P6ECDWE
厂商: Freescale Semiconductor
文件页数: 21/98页
文件大小: 0K
描述: IC MCU 8BIT EPROM 28-SOIC
标准包装: 26
系列: HC05
核心处理器: HC05
芯体尺寸: 8-位
速度: 2.1MHz
连通性: SIO
外围设备: POR,WDT
输入/输出数: 21
程序存储器容量: 4.5KB(4.5K x 8)
程序存储器类型: OTP
RAM 容量: 176 x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
数据转换器: A/D 4x8b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
包装: 管件
Operating Modes
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
28
Freescale Semiconductor
Figure 3-1. User Mode Pinout
3.4 Low-Power Modes
The MC68HC705P6A is capable of running in a low-power mode in each of its configurations. The WAIT
and STOP instructions provide three modes that reduce the power required for the MCU by stopping
various internal clocks and/or the on-chip oscillator. The SWAIT bit in the MOR is used to modify the
behavior of the STOP instruction from stop mode to halt mode. The flow of the stop, halt, and wait modes
is shown in Figure 3-2.
3.4.1 STOP Instruction
The STOP instruction can result in one of two modes of operation depending on the state of the SWAIT
bit in the MOR. If the SWAIT bit is clear, the STOP instruction will behave like a normal STOP instruction
in the M68HC05 Family and place the MCU in stop mode. If the SWAIT bit in the MOR is set, the STOP
instruction will behave like a WAIT instruction (with the exception of a brief delay at startup) and place the
MCU in halt mode.
3.4.1.1 Stop Mode
Execution of the STOP instruction when the SWAIT bit in the MOR is clear places the MCU in its lowest
power consumption mode. In stop mode, the internal oscillator is turned off, halting all internal processing,
including the COP watchdog timer. Execution of the STOP instruction automatically clears the I bit in the
condition code register so that the IRQ external interrupt is enabled. All other registers and memory
remain unaltered. All input/output lines remain unchanged.
The MCU can be brought out of stop mode only by an IRQ external interrupt or an externally generated
RESET. When exiting stop mode, the internal oscillator will resume after a 4064 internal clock cycle
oscillator stabilization delay.
NOTE
Execution of the STOP instruction when the SWAIT bit in the MOR is clear
will cause the oscillator to stop, and, therefore, disable the COP watchdog
timer. To avoid turning off the COP watchdog timer, stop mode should be
changed to halt mode by setting the SWAIT bit in the MOR. See 3.5 COP
Watchdog Timer Considerations for additional information.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RESET
IRQ/VPP
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
SDO/PB5
SDI/PB6
SCK/PB7
VSS
VDD
OSC1
OSC2
PD7/TCAP
TCMP
PD5
PC0
PC1
PC2
PC3/AD3
PC4/AD2
PC5/AD1
PC6/AD0
PC7/VREFH
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