参数资料
型号: MC7457TRX1000NC
厂商: Freescale Semiconductor
文件页数: 35/71页
文件大小: 0K
描述: IC MPU RISC 32BIT 483FCCBGA
标准包装: 36
系列: MPC74xx
处理器类型: 32-位 MPC74xx PowerPC
速度: 1.0GHz
电压: 1.1V
安装类型: 表面贴装
封装/外壳: 483-BCBGA,FCCBGA
供应商设备封装: 483-FCCBGA(29x29)
包装: 托盘
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8
Pinout Listings
Freescale Semiconductor
40
TEA
L1
Low
Input
BVSEL
TEST[0:3]
A12, B6, B10, E10
Input
BVSEL
12
TEST[4]
D10
Input
BVSEL
9
TMS
F1
High
Input
BVSEL
6
TRST
A5
Low
Input
BVSEL
6, 14
TS
L4
Low
I/O
BVSEL
3
TSIZ[0:2]
G6, F7, E7
High
Output
BVSEL
TT[0:4]
E5, E6, F6, E9, C5
High
I/O
BVSEL
WT
D3
Low
Output
BVSEL
VDD
H8, H10, H12, J7, J9, J11, J13, K8, K10, K12, K14, L7,
L9, L11, L13, M8, M10, M12
——
N/A
Notes:
1. OVDD supplies power to the processor bus, JTAG, and all control signals; and VDD supplies power to the processor core and
the PLL (after filtering to become AVDD). To program the I/O voltage, connect BVSEL to either GND (selects 1.8 V) or to
HRESET (selects 2.5 V). If used, the pull-down resistor should be less than 250
Ω. For actual recommended value of V
in or
supply voltages see Table 4.
2. Unused address pins must be pulled down to GND.
3. These pins require weak pull-up resistors (for example, 4.7 k
Ω) to maintain the control signals in the negated state after they
have been actively negated and released by the MPC7447 and other bus masters.
4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET going
high.
5. This signal must be negated during reset, by pull up to OVDD or negation by HRESET (inverse of HRESET), to ensure
proper operation.
6. Internal pull up on die.
7. Ignored in 60x bus mode.
8. These signals must be pulled down to GND if unused, or if the MPC7447 is in 60x bus mode.
9. These input signals are for factory use only and must be pulled down to GND for normal machine operation.
10.This test signal is recommended to be tied to HRESET; however, other configurations will not adversely affect performance.
11.These signals are for factory use only and must be left unconnected for normal machine operation.
12.These input signals are for factory use only and must be pulled up to OVDD for normal machine operation.
13.This pin can externally cause a performance monitor event. Counting of the event is enabled via software.
14.This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper operation.
Table 17. Pinout Listing for the MPC7457, 483 CBGA Package
Signal Name
Pin Number
Active
I/O
I/F Select 1
Notes
A[0:35]
E10, N4, E8, N5, C8, R2, A7, M2, A6, M1, A10, U2,
N2, P8, M8, W4, N6, U6, R5, Y4, P1, P4, R6, M7, N7,
AA3, U4, W2, W1, W3, V4, AA1, D10, J4, G10, D9
High
I/O
BVSEL
2
AACK
U1
Low
Input
BVSEL
AP[0:4]
L5, L6, J1, H2, G5
High
I/O
BVSEL
ARTRY
T2
Low
I/O
BVSEL
3
Table 16. Pinout Listing for the MPC7447, 360 CBGA Package (continued)
Signal Name
Pin Number
Active
I/O
I/F Select 1
Notes
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