- 您现在的位置：买卖IC网 > PDF目录45250 > MC7457VG1000LC (FREESCALE SEMICONDUCTOR INC) 32-BIT, 1000 MHz, RISC PROCESSOR, CBGA483 PDF资料下载
参数资料
| 型号： | MC7457VG1000LC |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1000 MHz, RISC PROCESSOR, CBGA483 |
| 封装： | 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PITCH, ROHS COMPLIANT, CERAMIC, BGA-483 |
| 文件页数： | 52/73页 |
| 文件大小： | 1715K |
| 代理商： | MC7457VG1000LC |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页当前第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 7
56
Freescale Semiconductor
System Design Information
If address or data parity is not used by the system, and the respective parity checking is disabled through
HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and
should be left unconnected by the system. If all parity generation is disabled through HID0, all parity
checking should also be disabled through HID0, and all parity pins may be left unconnected by the system.
The L3 interface does not normally require pull-up resistors. Unused L3_ADDR signals are driven low
when the SRAM is configured to be less than 1 M in size via L3CR. For example, L3_ADD[18] will be
driven low if the SRAM size is configured to be 2 M; likewise, L3_ADDR[18:17] will be driven low if
the SRAM size is configured to be 1 M.
9.7
JTAG Configuration Signals
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification, but is provided on all processors that implement the PowerPC architecture.
While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more
reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset.
Because the JTAG interface is also used for accessing the common on-chip processor (COP) function,
simply tying TRST to HRESET is not practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port of the processor, with some additional status
monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order
to fully control the processor. If the target system has independent reset sources, such as voltage monitors,
watchdog timers, power supply failures, or push-button switches, the COP reset signals must be merged
into these signals with logic.
The arrangement shown in Figure 26 allows the COP port to independently assert HRESET or TRST,
while ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not
be used, TRST should be tied to HRESET through a 0-Ω isolation resistor so that it is asserted when the
system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during
power-on. While Freescale recommends that the COP header be designed into the system as shown in
Figure 26, if this is not possible, the isolation resistor will allow future access to TRST in the case where
a JTAG interface may need to be wired onto the system in debug situations.
The COP header shown in Figure 26 adds many benefits—breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features are possible through this interface—and
can be as inexpensive as an unpopulated footprint for a header to be added when needed.
The COP interface has a standard header for connection to the target system, based on the 0.025"
square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has
pin 14 removed as a connector key.
There is no standardized way to number the COP header shown in Figure 26; consequently, many different
pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then
left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter
clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in
Figure 26 is common to all known emulators.
相关PDF资料 |
PDF描述 |
|---|---|
| MC7457RX867NC | 32-BIT, 867 MHz, RISC PROCESSOR, CBGA483 |
| MC7457VG867NC | 32-BIT, 867 MHz, RISC PROCESSOR, CBGA483 |
| MC7457RX1267LC | 32-BIT, 1267 MHz, RISC PROCESSOR, CBGA483 |
| MC7457VG733NC | 32-BIT, 733 MHz, RISC PROCESSOR, CBGA483 |
| MC74ACT125DR2 | ACT SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC7457VG1000NC | 功能描述:微处理器 - MPU APOLO7 RV1.2 1.1V 105C RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MC7457VG1267LC | 功能描述:微处理器 - MPU APOLO7 RV1.2 1.3V 105C RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MC7457VG733NC | 功能描述:IC MPU RISC 733MHZ 483FCCBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:MPC74xx 标准包装:1 系列:MPC85xx 处理器类型:32-位 MPC85xx PowerQUICC III 特点:- 速度:1.2GHz 电压:1.1V 安装类型:表面贴装 封装/外壳:783-BBGA，FCBGA 供应商设备封装:783-FCPBGA（29x29） 包装:托盘 |
| MC7457VG867NC | 功能描述:微处理器 - MPU APOLO7 RV1.2 1.1V 105C RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MC74A5-33SNTR | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
发布紧急采购，3分钟左右您将得到回复。