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参数资料
| 型号： | MC74HC109D |
| 厂商： | MOTOROLA INC |
| 元件分类： | 通用总线功能 |
| 英文描述： | Dual J-K Flip-Flop with Set and Reset |
| 中文描述： | HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 封装： | PLASTIC, SOIC-16 |
| 文件页数： | 2/5页 |
| 文件大小： | 186K |
| 代理商： | MC74HC109D |
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
2
(Plastic DIP or SOIC Package)
260
* Maximum Ratings are those values beyond which damage to the device may occur.
Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
0
400
VCC = 6.0 V
Symbol
Parameter
Test Conditions
V
25 C
Unit
Minimum High–Level Input
2.0
1.5
85 C
1.5
125 C
1.5
Voltage
20
μ
A
4.5
0.9
0.9
0.9
V
6.0
5.9
5.9
5.9
Vin = VIH or VIL
4.0 mA
3.98
3.84
3.70
|Iout|
4.5
6.0
0.1
0.1
0.1
4.0 mA
0.26
0.33
0.40
4.5
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout)
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
VCC.
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| MC74HC109N | Dual J-K Flip-Flop with Set and Reset |
| MC74HC10AD | Triple 3-Input NAND Gate |
| MC74HC10 | Triple 3-Input NAND Gate |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC74HC109DR2 | 制造商:Motorola Inc 功能描述:HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| MC74HC109N | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC74HC109ND | 制造商:Motorola Inc 功能描述: |
| MC74HC10AD | 制造商:Motorola Inc 功能描述: |
| MC74HC10ADG | 功能描述:逻辑门 TRIPLE 3-IN AND GATE RoHS:否 制造商:Texas Instruments 产品:OR 逻辑系列:LVC 栅极数量:2 线路数量（输入/输出）:2 / 1 高电平输出电流:- 16 mA 低电平输出电流:16 mA 传播延迟时间:3.8 ns 电源电压-最大:5.5 V 电源电压-最小:1.65 V 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:DCU-8 封装:Reel |
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