参数资料
型号: MC74HC32ADR2
厂商: ON Semiconductor
文件页数: 3/9页
文件大小: 0K
描述: IC GATE OR QUAD 2INPUT 14SOIC
标准包装: 1
系列: 74HC
逻辑类型: 或门
电路数: 4
输入数: 2
电源电压: 2 V ~ 6 V
电流 - 静态(最大值): 1µA
输出电流高,低: 5.2mA,5.2mA
逻辑电平 - 低: 0.5 V ~ 1.8 V
逻辑电平 - 高: 1.5 V ~ 4.2 V
额定电压和最大 CL 时的最大传播延迟: 13ns @ 6V,50pF
工作温度: -55°C ~ 125°C
安装类型: 表面贴装
供应商设备封装: 14-SOICN
封装/外壳: 14-SOIC(0.154",3.90mm 宽)
包装: 标准包装
其它名称: MC74HC32ADR2OSDKR
MC74HC32A
http://onsemi.com
3
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air,
Plastic DIP
SOIC Package
TSSOP Package
750
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
260
_C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, Vout
DC Input Voltage, Output Voltage (Referenced to
GND)
0
VCC
V
TA
Operating Temperature, All Package Types
– 55
+ 125
_C
tr, tf
Input Rise and Fall Time
VCC = 2.0 V
(Figure 1)
VCC = 4.5 V
VCC = 6.0 V
0
1000
500
400
ns
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
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