参数资料
型号: MC74HC4060ADR2G
厂商: ON Semiconductor
文件页数: 10/13页
文件大小: 0K
描述: IC COUNTER OSC 14STAGE 16SOIC
标准包装: 1
系列: 74HC
逻辑类型: 二进制计数器
方向:
元件数: 1
每个元件的位元数: 14
复位: 异步
计数速率: 50MHz
触发器类型: 负边沿
电源电压: 2 V ~ 6 V
工作温度: -55°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
供应商设备封装: 16-SOIC
包装: 标准包装
其它名称: MC74HC4060ADR2GOSDKR
MC74HC4060A
http://onsemi.com
6
PIN DESCRIPTIONS
INPUTS
Osc In (Pin 11)
Negativeedge triggering clock input. A hightolow
transition on this input advances the state of the counter. Osc
In may be driven by an external clock source.
Reset (Pin 12)
Activehigh reset. A high level applied to this input
asynchronously resets the counter to its zero state (forcing
all Q outputs low) and disables the oscillator.
OUTPUTS
Q4—Q10, Q12Q14 (Pins 7, 5, 4, 6, 13, 15, 1, 2, 3)
Activehigh outputs. Each Qn output divides the Clock
input frequency by 2N. The user should note the Q1, Q2, Q3
and Q11 are not available as outputs.
Osc Out 1, Osc Out 2 (Pins 9, 10)
Oscillator outputs. These pins are used in conjunction
with Osc In and the external components to form an
oscillator. When Osc In is being driven with an external
clock source, Osc Out 1 and Osc Out 2 must be left open
circuited. With the crystal oscillator configuration in Figure
6, Osc Out 2 must be left open circuited.
SWITCHING WAVEFORMS
tw
tf
Osc In
Q
VCC
GND
90%
50%
10%
tr
tw
90%
50%
10%
tPHL
1/fMAX
tPLH
tTLH
tTHL
Reset
VCC
GND
tPHL
50%
Figure 1.
Figure 2.
Q
VCC
GND
50%
Osc In
50%
trec
50%
Qn
VCC
GND
50%
Qn+1
CL*
*Includes all probe and jig capacitance
TEST
POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 3.
Figure 4. Test Circuit
tPLH
tPHL
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