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参数资料
型号： MC8640DTVU1000HC
厂商： Freescale Semiconductor
文件页数： 80/130页
文件大小： 0K
描述： MPU DUAL E600 1023-FCCBGA
标准包装： 1
系列： MPC86xx
处理器类型： 32-位 MPC86xx PowerPC
速度： 1.0GHz
电压： 1.05V
安装类型： 表面贴装
封装/外壳： 1023-BCBGA，FCCBGA
供应商设备封装： 1023-FCCBGA（33x33）
包装： 散装
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
53
JTAG
Figure 32 provides the AC test load for TDO and the boundary-scan outputs.
Figure 32. AC Test Load for the JTAG Interface
Figure 33 provides the JTAG clock input timing diagram.
Figure 33. JTAG Clock Input Timing Diagram
Output hold times:
Boundary-scan data
TDO
tJTKLDX
tJTKLOX
30
—
ns
5, 6
JTAG external clock to output high impedance:
Boundary-scan data
TDO
tJTKLDZ
tJTKLOZ
3
19
9
ns
5, 6
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50-
Ω load (see Figure 32).
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG
device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock
reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time
data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general,
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise
and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to tTCLK.
5. Non-JTAG signal output timing with respect to tTCLK.
6. Guaranteed by design.
Table 44. JTAG AC Timing Specifications (Independent of SYSCLK)1 (continued)
At recommended operating conditions (see Table 3).
Parameter
Symbol2
Min
Max
Unit
Notes
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
JTAG
tJTKHKL
tJTGR
External Clock
VM
tJTG
tJTGF
VM = Midpoint Voltage (OVDD/2)
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