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参数资料
型号： MC8641DTVU1000NC
厂商： Freescale Semiconductor
文件页数： 9/130页
文件大小： 0K
描述： MPU E600 DUAL CORE 1023-FCCBGA
标准包装： 1
系列： MPC86xx
处理器类型： 32-位 MPC86xx PowerPC
速度： 1.0GHz
电压： 0.95V
安装类型： 表面贴装
封装/外壳： 1023-BCBGA，FCCBGA
供应商设备封装： 1023-FCCBGA（33x33）
包装： 散装
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
106
Freescale Semiconductor
Clocking
18.2
MPX to SYSCLK PLL Ratio
The MPX clock is the clock that drives the MPX bus, and is also called the platform clock. The frequency
of the MPX is set using the following reset signals, as shown in Table 68:
SYSCLK input signal
Table 65. Memory Bus Clocking Specifications
Characteristic
Maximum Processor Core
Frequency
Unit
Notes
1000, 1250, 1333, 1500MHz
Min
Max
Memory bus clock frequency
200
300
MHz
1, 2
Notes:
1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to Section 18.2, “MPX to SYSCLK PLL Ratio,” and Section 18.3, “e600 to MPX clock PLL Ratio,”
for ratio settings.
2. The memory bus clock speed is half the DDR/DDR2 data rate, hence, half the MPX clock frequency.
Table 66. Platform/MPX bus Clocking Specifications
Characteristic
Maximum Processor Core
Frequency
Unit
Notes
1000, 1250, 1333, 1500MHz
Min
Max
Platform/MPX bus clock frequency
400
500-600
MHz
1, 2
Notes:
1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to Section 18.2, “MPX to SYSCLK PLL Ratio,” and Section 18.3, “e600 to MPX clock PLL Ratio,”
for ratio settings.
2. Platform/MPX frequencies between 400 and 500 MHz are not supported.
Table 67. Local Bus Clocking Specifications
Characteristic
Maximum Processor Core
Frequency
Unit
Notes
1000, 1250, 1333, 1500MHz
Min
Max
Local bus clock speed (for Local Bus Controller)
25
133
MHz
1
Notes:
1. The Local bus clock speed on LCLK[0:2] is determined by MPX clock divided by the Local Bus PLL ratio programmed in
LCRR[CLKDIV]. See the reference manual for the MPC8641D for more information on this.
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