参数资料
型号: MC8641VU1000NC
厂商: Freescale Semiconductor
文件页数: 105/130页
文件大小: 0K
描述: IC MPU SGL E600 CORE 994FCCBGA
标准包装: 1
系列: MPC86xx
处理器类型: 32-位 MPC86xx PowerPC
速度: 1.0GHz
电压: 0.95V
安装类型: 表面贴装
封装/外壳: 994-BCBGA,FCCBGA
供应商设备封装: 994-FCCBGA(33x33)
包装: 托盘
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
76
Freescale Semiconductor
PCI Express
provide additional margin to adequately compensate for the degraded minimum Receiver eye diagram
(shown in Figure 51) expected at the input Receiver based on some adequate combination of system
simulations and the Return Loss measured looking into the RX package and silicon. The RX eye diagram
must be aligned in time using the jitter median to locate the center of the eye diagram.
The eye diagram must be valid for any 250 consecutive UIs.
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX
UI.
NOTE
The reference impedance for return loss measurements is 50
Ω to ground for
both the D+ and D- line (that is, as measured by a Vector Network Analyzer
with 50
Ω probes—see Figure 52). Note that the series capacitors, CTX, are
optional for the return loss measurement.
Figure 51. Minimum Receiver Eye Timing and Voltage Compliance Specification
14.5.1
Compliance Test and Measurement Load
The AC timing and voltage parameters must be verified at the measurement point, as specified within 0.2
inches of the package pins, into a test/measurement load shown in Figure 52.
NOTE
The allowance of the measurement point to be within 0.2 inches of the
package pins is meant to acknowledge that package/board routing may
benefit from D+ and D– not being exactly matched in length at the package
pin boundary.
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