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| 型号： | MC908QL4MDWR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16 |
| 封装： | 1.27 MM PITCH, MS-013AA, SOIC-16 |
| 文件页数： | 77/226页 |
| 文件大小： | 2911K |
| 代理商： | MC908QL4MDWR2 |
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Slave LIN Interface Controller (SLIC) Module
MC68HC908QL4 Data Sheet, Rev. 7
168
Freescale Semiconductor
The error also comes into effect with transmitted bit times. Using the previous example with a SLCBT
value of 34, transmitted bits will appear as 34 SLIC clock periods long. This is one SLIC clock short of the
proper length. Depending on the frequency of the SLIC clock, one period of the SLIC clock might be a
large or a small fraction of one ideal bit time. Raising the frequency of the SLIC clock will reduce this error
relative to the ideal bit time, improving the resolution of the SLIC clock relative to the bit rate of the bus.
In any case, the error is still one SLIC clock cycle. Raising the SLIC clock frequency, however, requires
programming a higher value for SLCBT to maintain the same target bit rate.
Smaller values of SLCBT combined with higher values of the SLIC clock frequency (smaller clock period)
will give faster bit rates, but the SLIC clock period becomes an increasingly significant portion of one bit
time.
Because BTM mode does not perform any synchronization and relies on the accuracy of the data
provided by the user software to set its sample point and generate transmitted bits, the constraint on
maximum speeds is only limited to the limits imposed by the digital filter delay and the SLIC input clock.
Because the digital filter delay cannot be less than 16 SLIC clock cycles, the fastest possible pulse which
would pass the filter is 16 clock periods at 8 MHz, or 500,000 bits/second. The values shown in Table 14-7
are the same values shown in Table 14-8 and indicate the absolute fastest bit rates which could just pass
the minimum digital filter settings (prescaler = divide by 1) under perfect conditions.
Because perfect conditions are almost impossible to attain, more robust values must be chosen for bit
rates. For reliable communication, it is best to ensure that a bit time is no smaller 2x–3x longer than the
filter delay on the digital receive filter. This is true in LIN or BTM mode and ensures that valid data bits
which have been shortened due to ground shift, asymmetrical rise and fall times, etc., are accepted by
the filter without exception. This would translate to 2x to 3x reduction in the maximum speeds shown in
Table 14-7. Recommended maximum bit rates are shown in Table 14-8, and ensure that a single bit time
is at least twice the length of one filter delay value. If system noise is not adequately filtered out it might
be necessary to change the prescaler of the filter and lower the bit rate of the communication. If valid
communications are being absorbed by the filter, corrective action must be taken to ensure that either the
bit rate is reduced or whatever physical fault is causing bit times to shorten is corrected (ground offset,
asymmetrical rise/fall times, insufficient physical layer supply voltage, etc.).
Table 14-8. Recommended Maximum Bit Rates
for BTM Operation Due to Digital Filter
SLIC
Clock
(MHz)
Maximum BTM
Bit Rate with
Digital RX Filter
Set to
÷4
(Bits / Second)
Maximum BTM
Bit Rate with
Digital RX Filter
Set to
÷3
(Bits / Second)
Maximum BTM
Bit Rate with
Digital RX Filter
Set to
÷2
(Bits / Second)
Maximum BTM
Bit Rate with
Digital RX Filter
Set to
÷1
(Bits / Second)
8
62,500
83,333
120,000(1)
1. Bit rates over 120,000 bits per second are not recommended for BTM communications, as
physical layer delay between the TX and RX pins can cause the stop bit of a byte to be
missampled as the last data bit. This could result in a byte framing error.
120,000(1)
6.4
50,000
66,667
100,000
120,000(1)
4.8
37,500
50,000
75,000
120,000(1)
4
31,250
41,667
62,500
120,000(1)
3.2
25,000
33,333
50,000
100,000
2.4
18,750
25,000
37,500
75,000
2
15,625
20,833
31,250
62,500
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