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参数资料
| 型号： | MC92460ZU |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 40 CHANNEL(S), 66.7M bps, SERIAL COMM CONTROLLER, PBGA480 |
| 封装： | 37 X 37 MM, 1.70 MM HEIGHT, 1.27 MM PITCH, TBGA-480 |
| 文件页数： | 8/15页 |
| 文件大小： | 353K |
| 代理商： | MC92460ZU |
2
MC92460 HDLC Controller Hardware Specications
MOTOROLA
Features
Figure 1 shows a block diagram of the MC92460.
Figure 1. MC92460 Block Diagram
1.1
Features
The following is an overview of the MC92460 feature set:
Channels
— 40 full-duplex HDLC channels
— Programmable channel assignment (any logical channel to any signal)
— Each channel has a default of 64 buffer descriptors (Rx and Tx) but the number of buffer
descriptors per channel is congurable
Controllers
— Maximum throughput of 1919 Mbps; individual controllers operate up to 66.7 Mbps
— All communication controllers operate asynchronously
— Programmable frame size (maximum 65,535 bytes)
— Transparent memory access with internal memory controller
60x Bus
— MC92460 directly connects with a 64-bit data and 32-bit address 60x bus
— Supports 66.7 MHz 60x bus speed, with aggregate bandwidth of up to 1919 Mbps depending
Register interrupt
Bus Interface
MPC8260
dual-port RAM
32 Kbyte
SCU
32-byte x 80 FIFO
Communication
Buffer
(64-bit x 4kW)
BIST
SRAM
DMA
Arbiter
60x bus
Master Interface Unit
64-bit 66.7 MHz 3.3V
Rx FIFO
Tx FIFO
Flag/Abort/Idle
0-Insert/Delete
16 / 32 CRC
PLLs
HDLC
RxSD RxCK TxCK TxSD
JTAG
40 Channels
X 2
64-bit
MC92460
Two or more
MC92460s
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