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| 型号： | MC9328MXLVP15R2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 150 MHz, RISC PROCESSOR, PBGA225 |
| 封装： | 13 X 13 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-225 |
| 文件页数： | 79/90页 |
| 文件大小： | 1242K |
| 代理商： | MC9328MXLVP15R2 |
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Functional Description and Application Information
MC9328MXL Technical Data, Rev. 8
80
Freescale Semiconductor
4.14
CMOS Sensor Interface
The CMOS Sensor Interface (CSI) module consists of a control register to configure the interface timing,
a control register for statistic data generation, a status register, interface logic, a 32
× 32 image data receive
FIFO, and a 16
× 32 statistic data FIFO.
4.14.1
Gated Clock Mode
Figure 63 shows the timing diagram when the CMOS sensor output data is configured for negative edge
and the CSI is programmed to received data on the positive edge. Figure 64 shows the timing diagram
when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received
data in negative edge. The parameters for the timing diagrams are listed in Table 35.
28
STCK high to STXD high impedance
17.90
29.75
15.7
26.1
ns
29
SRXD setup time before SRCK low
1.14
–
1.0
–
ns
30
SRXD hold time after SRCK low
0
–
0
–
ns
Synchronous Internal Clock Operation (Port B Alternate Function2)
31
SRXD setup before STCK falling
18.81
–
16.5
–
ns
32
SRXD hold after STCK falling
0
–
0
–
ns
Synchronous External Clock Operation (Port B Alternate Function2)
33
SRXD setup before STCK falling
1.14
–
1.0
–
ns
34
SRXD hold after STCK falling
0
–
0
–
ns
1 All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
2 There are 2 set of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and Port B
alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed both at Port C primary
function and Port B alternate function. When SSI signals are configured as inputs, the SSI module selects the input based on
FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary function.
3
bl = bit length; wl = word length.
Table 34. SSI (Port B Alternate Function) Timing Parameter Table (Continued)
Ref
No.
Parameter
1.8 ± 0.1 V
3.0 ± 0.3 V
Unit
Minimum
Maximum
Minimum
Maximum
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MXL
Product
Family
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