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| 型号： | MC9328MXSCVP10R2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 100 MHz, MICROPROCESSOR, PBGA225 |
| 封装： | 13 X 13 MM, ROHS COMPLIANT, PLASTIC, MAPBGA-225 |
| 文件页数： | 55/68页 |
| 文件大小： | 1335K |
| 代理商： | MC9328MXSCVP10R2 |
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Functional Description and Application Information
MC9328MXS Technical Data, Rev. 2
Freescale Semiconductor
59
4.11
Synchronous Serial Interface
The transmit and receive sections of the SSI can be synchronous or asynchronous. In synchronous mode,
the transmitter and the receiver use a common clock and frame synchronization signal. In asynchronous
mode, the transmitter and receiver each have their own clock and frame synchronization signals.
Continuous or gated clock mode can be selected. In continuous mode, the clock runs continuously. In gated
clock mode, the clock functions only during transmission. The internal and external clock timing diagrams
Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of
I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is
typically used in star or ring-time division multiplex networks with other processors or codecs, allowing
interface to time division multiplexed networks without additional logic. Use of the gated clock is not
allowed in network mode. These distinctions result in the basic operating modes that allow the SSI to
communicate with a wide variety of devices.
Figure 50. SSI Transmitter Internal Clock Timing Diagram
Table 27. I2C Bus Timing Parameter Table
Ref No.
Parameter
1.8 ± 0.1 V
3.0 ± 0.3 V
Unit
Minimum
Maximum
Minimum
Maximum
1
Hold time (repeated) START condition
182
–
160
–
ns
2
Data hold time
01710150
ns
3
Data setup time
11.4
–
10
–
ns
4
HIGH period of the SCL clock
80
–
120
–
ns
5
LOW period of the SCL clock
480
–
320
–
ns
6
Setup time for STOP condition
182.4
–
160
–
ns
STCK Output
STFS (bl) Output
STFS (wl) Output
1
2
6
8
10
11
STXD Output
SRXD Input
32
31
4
12
Note: SRXD input in synchronous mode only.
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