参数资料
型号: MC9RS08LA8CLF
厂商: Freescale Semiconductor
文件页数: 8/33页
文件大小: 0K
描述: MCU 8BIT 8K FLASH W/LCD 48-LQFP
标准包装: 250
系列: RS08
核心处理器: RS08
芯体尺寸: 8-位
速度: 20MHz
连通性: SCI,SPI
外围设备: LCD,LVD,POR,PWM,WDT
输入/输出数: 31
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
数据转换器: A/D 6x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 48-LQFP
包装: 托盘
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
Electrical Characteristics
Freescale Semiconductor
16
Table 9. External Oscillator Specifications (Temperature Range = –40 to 85
°C Ambient)
Characteristic
Symbol
Min
Typical1
1 Data in Typical column was characterized at 3.0 V, 25 °C or is typical recommended value.
Max
Unit
Oscillator crystal or resonator (EREFS = 1)
Low range, (IREFS = x)
High range, FLL bypassed external (CLKS = 10, IREFS = x)
High range, FLL engaged external (CLKS = 00, IREFS = 0)
flo
fhi_byp
fhi_eng
32
1
38.4
10
kHz
MHz
Load capacitors
C1
C2
See Note 2
2 See crystal or resonator manufacturer’s recommendation.
Feedback resistor
Low range (32 kHz to 100 kHz)
High range (1 MHz to 16 MHz)
RF
10
1
M
Ω
M
Ω
Series resistor
Low range
Low Gain (HGO = 0)
High Gain (HGO = 1)
High range
Low Gain (HGO = 0)
High Gain (HGO = 1)
≥ 8 MHz
4 MHz
1 MHz
RS
0
100
0
10
20
k
Ω
Crystal start-up time 3, 4
Low range
High range
3 This parameter is characterized and not tested on each device.
4 Proper PC board layout procedures must be followed to achieve specifications.
t
CSTL
t
CSTH
500
4
ms
Square wave input clock frequency (EREFS = 0)
FLL bypass external (CLKS = 10)
FLL engaged external (CLKS = 00)
fextal
0
0.03125
20
5
MHz
Average internal reference frequency - untrimmed
fint_ut
25
31.25
41.66
kHz
Average internal reference frequency - trimmed
fint_t
31.25
39.0625
kHz
DCO output frequency range - untrimmed
fdco_ut
12.8
16
21.33
MHz
DCO output frequency range - trimmed
fdco_t
16
20
MHz
Resolution of trimmed DCO output frequency
at fixed voltage and temperature
Δfdco_res_t
——
±0.2
%fdco
Total deviation of trimmed DCO output frequency
over voltage and temperature
Δfdco_t
——
±2%fdco
FLL acquisition time 3,5
5 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used
as the reference, this specification assumes it is already running.
tacquire
——
1
ms
Long term Jitter 6 of DCO output clock
(averaged over 2ms interval)
CJitter
0.6
%fdco
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