
Time of Day Module (S08TODV1)
MC9S08LL64 MCU Series Reference Manual, Rev. 5
Freescale Semiconductor
317
16.4
Functional Description
This section provides a complete functional description of the TOD block, detailing the operation of the
design from the end-user perspective.
Before enabling the TOD module by asserting the TODEN bit in the TODC register, the proper clock
source and prescaler must be selected. Out of reset, the TOD module is configured with default settings,
but these settings are not optimal for every application. The default settings configure TOD operation for
an external 32.768 KHz oscillator. The TOD module provides a prescaler that allows several versatile
configuration settings for the input clock source Refer to the TODPS bit field description in
Table 16-3 to
see the different input clock sources that can be used.
The TOD clock source and the TOD prescaler must be modified only if the TOD is disabled. (TODEN = 0)
Selection of the proper clock source and prescaler settings is critical because these settings are used to
create the 4 Hz internal time base that is the basis for the TOD counter register. This ensures that
quarter-second and one-second interrupts will occur at the appropriate times. The match interrupt can be
used to generate interrupts at intervals that are multiple seconds.
Time of day can be maintained using software and the TOD module.
16.4.1
TOD Counter Register
The TOD counter is an 8-bit counter that starts at $00 and increments until $FF. After $FF is reached, the
counter rolls over to $00. This creates up to 256 counts.
A 4 Hz signal is the reference clock to the TOD counter. Each tick in the TOD counter is 0.25 of a second
and 4 ticks are a second. The second and quarter-second interrupts depend on proper initialization of the
TOD prescaler and clock source bits.
The TODR bit in the TODC register can be used to reset the TOD counter to $00. The TODR bit also resets
the 4 Hz generator ensuring that all TOD counting is starting at absolute zero time.
If the match function is enabled (MTCHEN = 1), the match flag is set when the TOD counter register
reaches the value in the TOD match register and the upper 6 bits of the TOD counter register are reset to 0.
16.4.2
TOD Match Value
The TOD match value is used to generate interrupts at multiple second intervals. The TOD match value is
a 6-bit value that can be set to any value from $00 to $3F. To enable match functionality, the MTCHEN
bit must be set. Always configure the TODM value before setting the MTCHEN bit, this ensures that the
next Match condition will occur at the desired setting.
When TODM is written,the lower 2 bits of the TODCNT are preloaded into MQSEC (the lower 2 bits of
the TODM register). When TODCNT reaches the value in the TOD match register, a match condition is
generated, the MTCHF is set, and the upper 6 bits of the TOD counter register are reset to 0.
For example, if the match value is set to $3C and the lower 2 bits of the TODCNT are 00 a match condition
will occur when the counter transitions from $EF to $F0.