
Chapter 5 Resets, Interrupts, and General System Control
MC9S08LL64 MCU Series Reference Manual, Rev. 5
Freescale Semiconductor
89
5.6.1
Power-On Reset Operation
When power is initially applied to the MCU, or when the supply voltage drops below the power-on reset
rearm voltage level, VPOR, the POR circuit will cause a reset condition. As the supply voltage rises, the
LVD circuit will hold the MCU in reset until the supply has risen above the low voltage detection low
threshold, VLVDL. Both the POR bit and the LVD bit in SRS are set following a POR.
5.6.2
Low-Voltage Detection (LVD) Reset Operation
The LVD can be configured to generate a reset upon detection of a low voltage condition by setting
LVDRE to 1. The low voltage detection threshold is determined by the LVDV bit. After an LVD reset has
occurred, the LVD system will hold the MCU in reset until the supply voltage has risen above the low
voltage detection threshold. The LVD bit in the SRS register is set following either an LVD reset or POR.
5.6.3
Low-Voltage Detection (LVD) Interrupt Operation
When a low voltage condition is detected and the LVD circuit is configured using SPMSC1 for interrupt
operation (LVDE set, LVDIE set, and LVDRE clear), then LVDF in SPMSC1 will be set and an LVD
interrupt request will occur. The LVDF bit is cleared by writing a 1 to the LVDACK bit in SPMSC1.
5.6.4
Low-Voltage Warning (LVW) Interrupt Operation
The LVD system has a low voltage warning flag (LVWF) to indicate to the user that the supply voltage is
approaching, but is above, the LVD voltage. The LVW also has an interrupt associated with it, enabled by
setting the LVWIE bit in the SPMSC3 register. If enabled, an LVW interrupt request will occur when the
LVWF is set. LVWF is cleared by writing a 1 to the LVWACK bit in SPMSC3. There are two user
selectable trip voltages for the LVW, one high (VLVWH) and one low (VLVWL). The trip voltage is selected
by LVWV in SPMSC3.
5.7
Peripheral Clock Gating
The MC9S08LL64 series include a clock gating system to manage the bus clock sources to the individual
peripherals. Using this system, the user can enable or disable the bus clock to each of the peripherals at the
clock source, eliminating unnecessary clocks to peripherals which are not in use and thereby reducing the
overall run and wait mode currents.
Out of reset, all peripheral clocks will be enabled. For lowest possible run or wait currents, user software
should disable the clock source to any peripheral not in use. The actual clock will be enabled or disabled
immediately following the write to the Clock Gating Control registers (SCGC1 and SCGC2). Any
peripheral with a gated clock cannot be used unless its clock is enabled. Writing to the registers of a
peripheral with a disabled clock has no effect.
NOTE
User software must disable the peripheral before disabling the clocks to the
peripheral. When clocks are re-enabled to a peripheral, the peripheral
registers need to be re-initialized by user software.