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参数资料
| 型号： | MC9S08MM64VLH64 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 48 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | 10 X 10 MM, ROHS COMPLIANT, LQFP-64 |
| 文件页数： | 33/52页 |
| 文件大小： | 548K |
| 代理商： | MC9S08MM64VLH64 |
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Electrical Characteristics
Freescale Semiconductor
39
2.12
SPI Characteristics
Table 22 and Figure 12 through Figure 15 describe the timing requirements for the SPI system.
Table 22. SPI Timing
No.1
1 Numbers in this column identify elements in Figure 12 through Figure 15.
Characteristic2
2 All timing is shown with respect to 20% V
DD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing
assumes slew rate control disabled and high drive strength enabled for SPI output pins.
Symbol
Min
Max
Unit
C
1
Operating frequency
Master
Slave
fop
fBus/2048
0
fBus/2
fBus/4
Hz
D
2
SPSCK period
Master
Slave
tSPSCK
2
4
2048
—
tcyc
D
3
Enable lead time
Master
Slave
tLead
1
2
1
—
tSPSCK
tcyc
D
4
Enable lag time
Master
Slave
tLag
1
2
1
—
tSPSCK
tcyc
D
5
Clock (SPSCK) high or low time
Master
Slave
tWSPSCK
tcyc –30
tcyc – 30
1024 tcyc
—
ns
D
6
Data setup time (inputs)
Master
Slave
tSU
15
—
ns
D
7
Data hold time (inputs)
Master
Slave
tHI
0
25
—
ns
D
8
Slave access time3
3 Time to data active from high-impedance state.
ta
—1
tcyc
D
9
Slave MISO disable time4
4 Hold time to high-impedance state.
tdis
—1
tcyc
D
10
Data valid (after SPSCK edge)
Master
Slave
tv
—
25
ns
D
11
Data hold time (outputs)
Master
Slave
tHO
0
—
ns
D
12
Rise time
Input
Output
tRI
tRO
—
tcyc – 25
25
ns
D
13
Fall time
Input
Output
tFI
tFO
—
tcyc – 25
25
ns
D
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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