参数资料
型号: MC9S12DB128VFU
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP80
封装: PLASTIC, LQFP-80
文件页数: 28/142页
文件大小: 6464K
代理商: MC9S12DB128VFU
Device User Guide — 9S12DT128DGV2/D V02.15
123
Freescale Semiconductor
And finally the frequency relationship is defined as
With the above values the resistance can be calculated. The example is shown for a loop bandwidth
fC=10KHz:
The capacitance Cs can now be calculated as:
The capacitance Cp should be chosen in the range of:
A.5.3.2 Jitter Information
The basic functionality of the PLL is shown in Figure A-3. With each transition of the clock fcmp, the
deviation from the reference clock fref is measured and input voltage to the VCO is adjusted
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-4.
n
f
VCO
f
ref
-------------
2
synr
1
+
()
==
= 50
R
2
π nf
C
KΦ
-----------------------------
=
= 2*
π*50*10kHz/(316.7Hz/)=9.9k =~ 10k
C
s
2
ζ
2
π f
C R
----------------------
0.516
f
C R
---------------
ζ 0.9
=
()
;
=
= 5.19nF =~ 4.7nF
C
s 20
C
p
C
s 10
≤≤
Cp = 470pF
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