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参数资料
| 型号： | MC9SA256BCFUR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP80 |
| 封装： | QFP-80 |
| 文件页数： | 39/102页 |
| 文件大小： | 1050K |
| 代理商： | MC9SA256BCFUR2 |
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MC9S12A256 Device Guide — V01.01
41
Section 4 Modes of Operation
4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12A256. Each mode has an
associated default memory map and external bus configuration.
Three low power modes exist for the device.
4.2 Modes of Operation
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset (Table 4-1). The MODC, MODB, and MODA bits in the MODE register show the current operating
mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA
pins are latched into these bits on the rising edge of the reset signal.
There are two basic types of operating modes:
1.
Normal modes: Some registers and bits are protected against accidental changes.
2.
Special modes: Allow greater access to protected control registers and bits for special purposes such
as testing.
A system development and debug feature, background debug mode (BDM), is available in all modes. In
special single-chip mode, BDM is active immediately after reset.
Some aspects of Port E are not mode dependent. Bit 1 of Port E is a general purpose input or the IRQ
interrupt input. IRQ can be enabled by bits in the CPU’s condition codes register but it is inhibited at reset
so this pin is initially configured as a simple input with a pull-up. Bit 0 of Port E is a general purpose input
or the XIRQ interrupt input. XIRQ can be enabled by bits in the CPU’s condition codes register but it is
inhibited at reset so this pin is initially configured as a simple input with a pull-up. The ESTR bit in the
EBICTL register is set to one by reset in any user mode.This assures that the reset vector can be fetched
Table 4-1 Mode Selection
MODC
MODB
MODA
Mode Description
000
Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all
other modes but a serial command is required to make BDM active.
0
1
Emulation Expanded Narrow, BDM allowed
0
1
0
Special Test (Expanded Wide), BDM allowed
0
1
Emulation Expanded Wide, BDM allowed
1
0
Normal Single Chip, BDM allowed
1
0
1
Normal Expanded Narrow, BDM allowed
110
Peripheral; BDM allowed but bus operations would cause bus conflicts
(must not be used)
1
Normal Expanded Wide, BDM allowed
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