MC9S12DJ64 Device User Guide — V01.02
28
Table 2-1 Signal Properties
Pin Name
Function 1
Pin Name
Function 2
Pin Name
Function 3
Pin Name
Function 4
Description
EXTAL
—
Oscillator Pins
XTAL
—
RESET
—
External Reset
TEST
—
Test Input
VREGEN
—
Voltage Regulator Enable Input
XFC
—
PLL Loop Filter
BKGD
TAGHI
MODC
—
Background Debug, Tag High, Mode Input
PAD15
AN15
ETRIG1
—
Port AD Input, Analog Input AN7 of ATD1,
External Trigger Input of ATD1
PAD[14:08]
AN[14:08]
—
Port AD Inputs, Analog Inputs AN[6:0] of
ATD1
PAD07
AN07
ETRIG0
—
Port AD Input, Analog Input AN7 of ATD0,
External Trigger Input of ATD0
PAD[06:00]
AN[06:00]
—
Port AD Inputs, Analog Inputs AN[6:0] of
ATD0
PA[7:0]
ADDR[15:8]/
DATA[15:8]
—
Port A I/O, Multiplexed Address/Data
PB[7:0]
ADDR[7:0]/
DATA[7:0]
—
Port B I/O, Multiplexed Address/Data
PE7
NOACC
XCLKS
—
Port E I/O, Access, Clock Select
PE6
IPIPE1
MODB
—
Port E I/O, Pipe Status, Mode Input
PE5
IPIPE0
MODA
—
Port E I/O, Pipe Status, Mode Input
PE4
ECLK
—
Port E I/O, Bus Clock Output
PE3
LSTRB
TAGLO
—
Port E I/O, Byte Strobe, Tag Low
PE2
R/W
—
Port E I/O, R/W in expanded modes
PE1
IRQ
—
Port E Input, Maskable Interrupt
PE0
XIRQ
—
Port E Input, Non Maskable Interrupt
PH7
KWH7
——
Port H I/O, Interrupt
PH6
KWH6
——
Port H I/O, Interrupt
PH5
KWH5
——
Port H I/O, Interrupt
PH4
KWH4
——
Port H I/O, Interrupt
PH3
KWH3
——
Port H I/O, Interrupt
PH2
KWH2
——
Port H I/O, Interrupt
PH1
KWH1
——
Port H I/O, Interrupt
PH0
KWH0
——
Port H I/O, Interrupt
PJ7
KWJ7
SCL
TXCAN0
Port J I/O, Interrupt, SCL of IIC, TX of CAN0
PJ6
KWJ6
SDA
RXCAN0
Port J I/O, Interrupt, SDA of IIC, RX of CAN0
PJ[1:0]
KWJ[1:0]
—
Port J I/O, Interrupts
PK7
ECS
ROMONE
—
Port K I/O, Emulation Chip Select, ROM On
Enable
PK[5:0]
XADDR[19:14]
—
Port K I/O, Extended Addresses
PM7
—
Port M I/O
PM6
—
Port M I/O
PM5
TXCAN0
SCK
—
Port M I/O, TX of CAN0, SCK of SPI0