参数资料
型号: MCF51QE96CLK
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 50.33 MHz, MICROCONTROLLER, PQFP80
封装: 14 X 14 MM, ROHS COMPLIANT, LQFP-80
文件页数: 15/38页
文件大小: 978K
代理商: MCF51QE96CLK
MCF51QE128 Series Data Sheet, Rev. 7
Electrical Characteristics
Freescale Semiconductor
22
Figure 14. Reset Timing
Figure 15. IRQ/KBIPx Timing
7D
IRQ pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
2 x tcyc
ns
8D
Keyboard interrupt pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
2 x tcyc
ns
9C
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
8
31
ns
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
7
24
ns
10
Voltage regulator recovery time
tVRR
—4
μs
1 Typical values are based on characterization data at V
DD = 3.0V, 25°C unless otherwise stated.
2 This is the shortest pulse that is guaranteed to be recognized as a reset or interrupt pin request. Shorter pulses are not
guaranteed to override reset requests from internal sources.
3 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t
MSH after VDD
rises above VLVD.
4 This is the minimum assertion time in which the interrupt may be recognized. The correct protocol is to assert the interrupt
request until it is explicitly negated by the interrupt service routine.
5 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40°C to 85°C.
Table 13. Control Timing (continued)
Num
C
Rating
Symbol
Min
Typ1
Max
Unit
textrst
RESET PIN
tIHIL
KBIPx
tILIH
IRQ/KBIPx
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